arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk

The PCIe Gen4x2 PHY found in the SM8650 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-3-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 819f6eadba07453f962977a67331cf17c6b95741..fa6c3b397f2d63d0a7cf185d2bbaaead2d7d6681 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -641,10 +641,6 @@
        status = "okay";
 };
 
-&pcie_1_phy_aux_clk {
-       clock-frequency = <1000>;
-};
-
 &pcie0 {
        wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
        perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index f93de21a26ad23ec69783f8b23ae8431b4bdd8d9..98f6a272ce5abfaca3d692dbfa113c6c8fc2e82f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -834,10 +834,6 @@
        data-lanes = <0 1>;
 };
 
-&pcie_1_phy_aux_clk {
-       clock-frequency = <1000>;
-};
-
 &pcie0 {
        wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
        perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index dacfade2ceafac798ed182fe6085338f01babf73..518fa4c4f3032bbdc8fd01b02d3d83341f04a386 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -60,11 +60,6 @@
                        clock-mult = <1>;
                        clock-div = <2>;
                };
-
-               pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
-                       compatible = "fixed-clock";
-                       #clock-cells = <0>;
-               };
        };
 
        cpus {
@@ -758,8 +753,8 @@
                                 <&bi_tcxo_ao_div2>,
                                 <&sleep_clk>,
                                 <&pcie0_phy>,
-                                <&pcie1_phy>,
-                                <&pcie_1_phy_aux_clk>,
+                                <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+                                <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
                                 <&ufs_mem_phy 0>,
                                 <&ufs_mem_phy 1>,
                                 <&ufs_mem_phy 2>,
@@ -2467,8 +2462,8 @@
 
                        power-domains = <&gcc PCIE_1_PHY_GDSC>;
 
-                       #clock-cells = <0>;
-                       clock-output-names = "pcie1_pipe_clk";
+                       #clock-cells = <1>;
+                       clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
 
                        #phy-cells = <0>;