.*: Assembler messages:
-.*Error: illegal operands vd must be multiple of 2 `vwcvtu.x.x.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vwcvtu.x.x.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vwcvtu.x.x.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vwcvtu.x.x.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwcvt.x.x.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vwcvt.x.x.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vwcvt.x.x.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vwcvt.x.x.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwaddu.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwaddu.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwaddu.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwaddu.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwaddu.vx v1,v2,a1'
.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vx v2,v2,a1'
-.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwaddu.vx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwaddu.wv v1,v2,v4'
-.*Error: illegal operands vs2 must be multiple of 2 `vwaddu.wv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwaddu.wv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwaddu.wv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwaddu.wv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwaddu.wx v1,v2,a1'
-.*Error: illegal operands vs2 must be multiple of 2 `vwaddu.wx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwaddu.wx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsubu.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwsubu.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwsubu.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwsubu.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsubu.vx v1,v2,a1'
.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vx v2,v2,a1'
-.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwsubu.vx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsubu.wv v1,v2,v4'
-.*Error: illegal operands vs2 must be multiple of 2 `vwsubu.wv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwsubu.wv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwsubu.wv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwsubu.wv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsubu.wx v1,v2,a1'
-.*Error: illegal operands vs2 must be multiple of 2 `vwsubu.wx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwsubu.wx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwadd.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwadd.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwadd.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwadd.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwadd.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwadd.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwadd.vx v1,v2,a1'
.*Error: illegal operands vd cannot overlap vs2 `vwadd.vx v2,v2,a1'
-.*Error: illegal operands vd cannot overlap vs2 `vwadd.vx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwadd.vx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwadd.wv v1,v2,v4'
-.*Error: illegal operands vs2 must be multiple of 2 `vwadd.wv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwadd.wv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwadd.wv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwadd.wv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwadd.wx v1,v2,a1'
-.*Error: illegal operands vs2 must be multiple of 2 `vwadd.wx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwadd.wx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsub.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwsub.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwsub.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwsub.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwsub.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwsub.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsub.vx v1,v2,a1'
.*Error: illegal operands vd cannot overlap vs2 `vwsub.vx v2,v2,a1'
-.*Error: illegal operands vd cannot overlap vs2 `vwsub.vx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwsub.vx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsub.wv v1,v2,v4'
-.*Error: illegal operands vs2 must be multiple of 2 `vwsub.wv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwsub.wv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwsub.wv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwsub.wv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwsub.wx v1,v2,a1'
-.*Error: illegal operands vs2 must be multiple of 2 `vwsub.wx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwsub.wx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmul.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwmul.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwmul.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwmul.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwmul.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwmul.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmul.vx v1,v2,a1'
.*Error: illegal operands vd cannot overlap vs2 `vwmul.vx v2,v2,a1'
-.*Error: illegal operands vd cannot overlap vs2 `vwmul.vx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwmul.vx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmulu.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwmulu.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwmulu.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwmulu.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmulu.vx v1,v2,a1'
.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vx v2,v2,a1'
-.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwmulu.vx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmulsu.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwmulsu.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwmulsu.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwmulsu.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmulsu.vx v1,v2,a1'
.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vx v2,v2,a1'
-.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vx v2,v3,a1'
.*Error: illegal operands vd cannot overlap vm `vwmulsu.vx v0,v2,a1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmaccu.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwmaccu.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwmaccu.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwmaccu.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmaccu.vx v1,a1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vx v2,a1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vx v2,a1,v3'
.*Error: illegal operands vd cannot overlap vm `vwmaccu.vx v0,a1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmacc.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwmacc.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwmacc.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwmacc.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmacc.vx v1,a1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vx v2,a1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vx v2,a1,v3'
.*Error: illegal operands vd cannot overlap vm `vwmacc.vx v0,a1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmaccsu.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs1 `vwmaccsu.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vwmaccsu.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmaccsu.vx v1,a1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vx v2,a1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vx v2,a1,v3'
.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vx v0,a1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vwmaccus.vx v1,a1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vwmaccus.vx v2,a1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vwmaccus.vx v2,a1,v3'
.*Error: illegal operands vd cannot overlap vm `vwmaccus.vx v0,a1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwadd.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwadd.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwadd.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwadd.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwadd.vf v1,v2,fa1'
.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vf v2,v2,fa1'
-.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vf v2,v3,fa1'
.*Error: illegal operands vd cannot overlap vm `vfwadd.vf v0,v2,fa1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwadd.wv v1,v2,v4'
-.*Error: illegal operands vs2 must be multiple of 2 `vfwadd.wv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwadd.wv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwadd.wv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwadd.wv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwsub.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwsub.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwsub.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwsub.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwsub.vf v1,v2,fa1'
.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
-.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v3,fa1'
.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwsub.wv v1,v2,v4'
-.*Error: illegal operands vs2 must be multiple of 2 `vfwsub.wv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwsub.wv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwsub.wv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwsub.wv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwmul.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs2 `vfwmul.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vfwmul.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwmul.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwmul.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwmul.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwsub.vf v1,v2,fa1'
.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
-.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v3,fa1'
.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwmacc.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwmacc.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwmacc.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwmacc.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwmacc.vf v1,fa1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vf v2,fa1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vf v2,fa1,v3'
.*Error: illegal operands vd cannot overlap vm `vfwmacc.vf v0,fa1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwnmacc.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwnmacc.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwnmacc.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwnmacc.vf v1,fa1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vf v2,fa1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vf v2,fa1,v3'
.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vf v0,fa1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwmsac.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwmsac.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwmsac.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwmsac.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwmsac.vf v1,fa1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vf v2,fa1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vf v2,fa1,v3'
.*Error: illegal operands vd cannot overlap vm `vfwmsac.vf v0,fa1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwnmsac.vv v1,v2,v4'
.*Error: illegal operands vd cannot overlap vs1 `vfwnmsac.vv v2,v2,v4'
-.*Error: illegal operands vd cannot overlap vs1 `vfwnmsac.vv v2,v3,v4'
.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vv v4,v2,v4'
-.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vv v4,v2,v5'
.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vv v0,v2,v4,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwnmsac.vf v1,fa1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vf v2,fa1,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vf v2,fa1,v3'
.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vf v0,fa1,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwcvt.xu.f.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.xu.f.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.xu.f.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vfwcvt.xu.f.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwcvt.x.f.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.x.f.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.x.f.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vfwcvt.x.f.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwcvt.rtz.xu.f.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.xu.f.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.xu.f.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwcvt.rtz.x.f.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.x.f.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.x.f.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.x.f.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.xu.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.xu.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.xu.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.xu.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.x.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.x.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.x.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.x.v v0,v2,v0.t'
-.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.f.v v1,v2'
.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.f.v v2,v2'
-.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.f.v v2,v3'
.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.f.v v0,v2,v0.t'
# Vector Widening Integer Add/Subtract
# vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
- vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
+ vwcvtu.x.x.v v1, v2 # OK since fractional LMUL. vd should be multiple of 2
vwcvtu.x.x.v v2, v2 # vd overlap vs2
- vwcvtu.x.x.v v2, v3 # vd overlap vs2
+ vwcvtu.x.x.v v2, v3 # OK since fractional LMUL. vd overlap vs2
vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
# vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
vwcvt.x.x.v v2, v3
vwcvt.x.x.v v0, v2, v0.t
- vwaddu.vv v1, v2, v4 # vd should be multiple of 2
+ vwaddu.vv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vwaddu.vv v2, v2, v4 # vd overlap vs2
- vwaddu.vv v2, v3, v4 # vd overlap vs2
+ vwaddu.vv v2, v3, v4 # OK since fractional LMUL. vd overlap vs2
vwaddu.vv v4, v2, v4 # vd overlap vs1
- vwaddu.vv v4, v2, v5 # vd overlap vs1
+ vwaddu.vv v4, v2, v5 # OK since fractional LMUL. vd overlap vs1
vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
- vwaddu.vx v1, v2, a1 # vd should be multiple of 2
+ vwaddu.vx v1, v2, a1 # OK since fractional LMUL. vd should be multiple of 2
vwaddu.vx v2, v2, a1 # vd overlap vs2
- vwaddu.vx v2, v3, a1 # vd overlap vs2
+ vwaddu.vx v2, v3, a1 # OK since fractional LMUL. vd overlap vs2
vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
- vwaddu.wv v1, v2, v4 # vd should be multiple of 2
+ vwaddu.wv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vwaddu.wv v2, v2, v4 # OK
- vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
+ vwaddu.wv v2, v3, v4 # OK since fractional LMUL. vs2 should be multiple of 2
vwaddu.wv v4, v2, v4 # vd overlap vs1
- vwaddu.wv v4, v2, v5 # vd overlap vs1
+ vwaddu.wv v4, v2, v5 # OK since fractional LMUL. vd overlap vs1
vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
- vwaddu.wx v1, v2, a1 # vd should be multiple of 2
+ vwaddu.wx v1, v2, a1 # OK since fractional LMUL. vd should be multiple of 2
vwaddu.wx v2, v2, a1 # OK
- vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
+ vwaddu.wx v2, v3, a1 # OK since fractional LMUL. vs2 should be multiple of 2
vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
vwsubu.vv v1, v2, v4
# Vector Widening Integer Multiply Instructions
- vwmul.vv v1, v2, v4 # vd should be multiple of 2
+ vwmul.vv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vwmul.vv v2, v2, v4 # vd overlap vs2
- vwmul.vv v2, v3, v4 # vd overlap vs2
+ vwmul.vv v2, v3, v4 # OK since fractional LMUL. vd overlap vs2
vwmul.vv v4, v2, v4 # vd overlap vs1
- vwmul.vv v4, v2, v5 # vd overlap vs1
+ vwmul.vv v4, v2, v5 # OK since fractional LMUL. vd overlap vs1
vwmul.vv v0, v2, v4, v0.t # vd overlap vm
- vwmul.vx v1, v2, a1 # vd should be multiple of 2
+ vwmul.vx v1, v2, a1 # OK since fractional LMUL. vd should be multiple of 2
vwmul.vx v2, v2, a1 # vd overlap vs2
- vwmul.vx v2, v3, a1 # vd overlap vs2
+ vwmul.vx v2, v3, a1 # OK since fractional LMUL. vd overlap vs2
vwmul.vx v0, v2, a1, v0.t # vd overlap vm
vwmulu.vv v1, v2, v4
# Vector Widening Integer Multiply-Add Instructions
- vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
+ vwmaccu.vv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vwmaccu.vv v2, v2, v4 # vd overlap vs1
- vwmaccu.vv v2, v3, v4 # vd overlap vs1
+ vwmaccu.vv v2, v3, v4 # OK since fractional LMUL. vd overlap vs1
vwmaccu.vv v4, v2, v4 # vd overlap vs2
- vwmaccu.vv v4, v2, v5 # vd overlap vs2
+ vwmaccu.vv v4, v2, v5 # OK since fractional LMUL. vd overlap vs2
vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
- vwmaccu.vx v1, a1, v2 # vd should be multiple of 2
+ vwmaccu.vx v1, a1, v2 # OK since fractional LMUL. vd should be multiple of 2
vwmaccu.vx v2, a1, v2 # vd overlap vs2
- vwmaccu.vx v2, a1, v3 # vd overlap vs2
+ vwmaccu.vx v2, a1, v3 # OK since fractional LMUL. vd overlap vs2
vwmaccu.vx v0, a1, v2, v0.t # vd overlap vm
vwmacc.vv v1, v2, v4
vwmaccsu.vx v2, a1, v3
vwmaccsu.vx v0, a1, v2, v0.t
- vwmaccus.vx v1, a1, v2 # vd should be multiple of 2
+ vwmaccus.vx v1, a1, v2 # OK since fractional LMUL. vd should be multiple of 2
vwmaccus.vx v2, a1, v2 # vd overlap vs2
- vwmaccus.vx v2, a1, v3 # vd overlap vs2
+ vwmaccus.vx v2, a1, v3 # OK since fractional LMUL. vd overlap vs2
vwmaccus.vx v0, a1, v2, v0.t # vd overlap vm
# Vector Widening Floating-Point Add/Subtract Instructions
- vfwadd.vv v1, v2, v4 # vd should be multiple of 2
+ vfwadd.vv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vfwadd.vv v2, v2, v4 # vd overlap vs2
- vfwadd.vv v2, v3, v4 # vd overlap vs2
+ vfwadd.vv v2, v3, v4 # OK since fractional LMUL. vd overlap vs2
vfwadd.vv v4, v2, v4 # vd overlap vs1
- vfwadd.vv v4, v2, v5 # vd overlap vs1
+ vfwadd.vv v4, v2, v5 # OK since fractional LMUL. vd overlap vs1
vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
- vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
+ vfwadd.vf v1, v2, fa1 # OK since fractional LMUL. vd should be multiple of 2
vfwadd.vf v2, v2, fa1 # vd overlap vs2
- vfwadd.vf v2, v3, fa1 # vd overlap vs2
+ vfwadd.vf v2, v3, fa1 # OK since fractional LMUL. vd overlap vs2
vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
- vfwadd.wv v1, v2, v4 # vd should be multiple of 2
+ vfwadd.wv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vfwadd.wv v2, v2, v4 # OK
- vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
+ vfwadd.wv v2, v3, v4 # OK since fractional LMUL. vs2 should be multiple of 2
vfwadd.wv v4, v2, v4 # vd overlap vs1
- vfwadd.wv v4, v2, v5 # vd overlap vs1
+ vfwadd.wv v4, v2, v5 # OK since fractional LMUL. vd overlap vs1
vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
vfwsub.vv v1, v2, v4
# Vector Widening Floating-Point Multiply
- vfwmul.vv v1, v2, v4 # vd should be multiple of 2
+ vfwmul.vv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vfwmul.vv v2, v2, v4 # vd overlap vs2
- vfwmul.vv v2, v3, v4 # vd overlap vs2
+ vfwmul.vv v2, v3, v4 # OK since fractional LMUL. vd overlap vs2
vfwmul.vv v4, v2, v4 # vd overlap vs1
- vfwmul.vv v4, v2, v5 # vd overlap vs1
+ vfwmul.vv v4, v2, v5 # OK since fractional LMUL. vd overlap vs1
vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
- vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
+ vfwsub.vf v1, v2, fa1 # OK since fractional LMUL. vd should be multiple of 2
vfwsub.vf v2, v2, fa1 # vd overlap vs2
- vfwsub.vf v2, v3, fa1 # vd overlap vs2
+ vfwsub.vf v2, v3, fa1 # OK since fractional LMUL. vd overlap vs2
vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
# Vector Widening Floating-Point Fused Multiply-Add Instructions
- vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
+ vfwmacc.vv v1, v2, v4 # OK since fractional LMUL. vd should be multiple of 2
vfwmacc.vv v2, v2, v4 # vd overlap vs1
- vfwmacc.vv v2, v3, v4 # vd overlap vs1
+ vfwmacc.vv v2, v3, v4 # OK since fractional LMUL. vd overlap vs1
vfwmacc.vv v4, v2, v4 # vd overlap vs2
- vfwmacc.vv v4, v2, v5 # vd overlap vs2
+ vfwmacc.vv v4, v2, v5 # OK since fractional LMUL. vd overlap vs2
vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
- vfwmacc.vf v1, fa1, v2 # vd should be multiple of 2
+ vfwmacc.vf v1, fa1, v2 # OK since fractional LMUL. vd should be multiple of 2
vfwmacc.vf v2, fa1, v2 # vd overlap vs2
- vfwmacc.vf v2, fa1, v3 # vd overlap vs2
+ vfwmacc.vf v2, fa1, v3 # OK since fractional LMUL. vd overlap vs2
vfwmacc.vf v0, fa1, v2, v0.t # vd overlap vm
vfwnmacc.vv v1, v2, v4
# Widening Floating-Point/Integer Type-Convert Instructions
- vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
+ vfwcvt.xu.f.v v1, v2 # OK since fractional LMUL. vd should be multiple of 2
vfwcvt.xu.f.v v2, v2 # vd overlap vs2
- vfwcvt.xu.f.v v2, v3 # vd overlap vs2
+ vfwcvt.xu.f.v v2, v3 # OK since fractional LMUL. vd overlap vs2
vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
vfwcvt.x.f.v v1, v2
vfwcvt.x.f.v v2, v2
/* These are used to check the vector constraints. */
static int
-match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
- insn_t insn,
- int constraints,
- const char **error)
+match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
+ insn_t insn,
+ int constraints,
+ const char **error)
{
int vd = (insn & MASK_VD) >> OP_SH_VD;
int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
if (!constraints || error == NULL)
return match_opcode (op, insn, 0, NULL);
- if ((vd % 2) != 0)
- *error = "illegal operands vd must be multiple of 2";
- else if (vs1 >= vd && vs1 <= (vd + 1))
+ if (vs1 == vd)
*error = "illegal operands vd cannot overlap vs1";
- else if (vs2 >= vd && vs2 <= (vd + 1))
+ else if (vs2 == vd)
*error = "illegal operands vd cannot overlap vs2";
- else if (!vm && vm >= vd && vm <= (vd + 1))
- *error = "illegal operands vd cannot overlap vm";
else
return match_opcode (op, insn, 0, NULL);
return 0;
}
static int
-match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
- insn_t insn,
- int constraints,
- const char **error)
+match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
+ insn_t insn,
+ int constraints,
+ const char **error)
{
int vd = (insn & MASK_VD) >> OP_SH_VD;
int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- if (!constraints || error == NULL)
- return match_opcode (op, insn, 0, NULL);
-
- if ((vd % 2) != 0)
- *error = "illegal operands vd must be multiple of 2";
- else if ((vs2 % 2) != 0)
- *error = "illegal operands vs2 must be multiple of 2";
- else if (vs1 >= vd && vs1 <= (vd + 1))
- *error = "illegal operands vd cannot overlap vs1";
- else if (!vm && vm >= vd && vm <= (vd + 1))
- *error = "illegal operands vd cannot overlap vm";
- else
- return match_opcode (op, insn, 0, NULL);
- return 0;
-}
-
-static int
-match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- insn_t insn,
- int constraints,
- const char **error)
-{
- int vd = (insn & MASK_VD) >> OP_SH_VD;
- int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
-
- if (!constraints || error == NULL)
- return match_opcode (op, insn, 0, NULL);
-
- if ((vd % 2) != 0)
- *error = "illegal operands vd must be multiple of 2";
- else if (vs2 >= vd && vs2 <= (vd + 1))
- *error = "illegal operands vd cannot overlap vs2";
- else if (!vm && vm >= vd && vm <= (vd + 1))
- *error = "illegal operands vd cannot overlap vm";
- else
- return match_opcode (op, insn, 0, NULL);
- return 0;
-}
-
-static int
-match_widen_vd_neq_vm (const struct riscv_opcode *op,
- insn_t insn,
- int constraints,
- const char **error)
-{
- int vd = (insn & MASK_VD) >> OP_SH_VD;
- int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
-
- if (!constraints || error == NULL)
- return match_opcode (op, insn, 0, NULL);
-
- if ((vd % 2) != 0)
- *error = "illegal operands vd must be multiple of 2";
- else if ((vs2 % 2) != 0)
- *error = "illegal operands vs2 must be multiple of 2";
- else if (!vm && vm >= vd && vm <= (vd + 1))
- *error = "illegal operands vd cannot overlap vm";
- else
- return match_opcode (op, insn, 0, NULL);
- return 0;
-}
-
-static int
-match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- insn_t insn,
- int constraints,
- const char **error)
-{
- int vd = (insn & MASK_VD) >> OP_SH_VD;
- int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
-
- if (!constraints || error == NULL)
- return match_opcode (op, insn, 0, NULL);
-
- if ((vs2 % 2) != 0)
- *error = "illegal operands vd must be multiple of 2";
- else if (vd >= vs2 && vd <= (vs2 + 1))
- *error = "illegal operands vd cannot overlap vs2";
- else if (!vm && vd >= vm && vd <= (vm + 1))
- *error = "illegal operands vd cannot overlap vm";
- else
- return match_opcode (op, insn, 0, NULL);
- return 0;
-}
-
-static int
-match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
- insn_t insn,
- int constraints,
- const char **error)
-{
- int vd = (insn & MASK_VD) >> OP_SH_VD;
- int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
-
if (!constraints || error == NULL)
return match_opcode (op, insn, 0, NULL);
*error = "illegal operands vd cannot overlap vs1";
else if (vs2 == vd)
*error = "illegal operands vd cannot overlap vs2";
+ else if (!vm && vm == vd)
+ *error = "illegal operands vd cannot overlap vm";
else
return match_opcode (op, insn, 0, NULL);
return 0;
}
static int
-match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
- insn_t insn,
- int constraints,
- const char **error)
+match_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
+ insn_t insn,
+ int constraints,
+ const char **error)
{
int vd = (insn & MASK_VD) >> OP_SH_VD;
int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
if (!constraints || error == NULL)
if (vs1 == vd)
*error = "illegal operands vd cannot overlap vs1";
- else if (vs2 == vd)
- *error = "illegal operands vd cannot overlap vs2";
else if (!vm && vm == vd)
*error = "illegal operands vd cannot overlap vm";
else
{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
-{"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
-{"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
-
-{"vwaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
-{"vwaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
-{"vwsubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
-{"vwsubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
-{"vwadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
-{"vwadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
-{"vwsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
-{"vwsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
-{"vwaddu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
-{"vwaddu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
-{"vwsubu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
-{"vwsubu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
-{"vwadd.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
-{"vwadd.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
-{"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
-{"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
+{"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_vd_neq_vs2_neq_vm, INSN_ALIAS },
+{"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_vd_neq_vs2_neq_vm, INSN_ALIAS },
+
+{"vwaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+{"vwaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_vd_neq_vs2_neq_vm, 0 },
+{"vwsubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+{"vwsubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_vd_neq_vs2_neq_vm, 0 },
+{"vwadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+{"vwadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_vd_neq_vs2_neq_vm, 0 },
+{"vwsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+{"vwsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_vd_neq_vs2_neq_vm, 0 },
+{"vwaddu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_vd_neq_vs1_neq_vm, 0 },
+{"vwaddu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_vd_neq_vm, 0 },
+{"vwsubu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_vd_neq_vs1_neq_vm, 0 },
+{"vwsubu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_vd_neq_vm, 0 },
+{"vwadd.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_vd_neq_vs1_neq_vm, 0 },
+{"vwadd.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_vd_neq_vm, 0 },
+{"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_vd_neq_vs1_neq_vm, 0 },
+{"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_vd_neq_vm, 0 },
{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
-{"vncvt.x.x.w",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
+{"vncvt.x.x.w",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_opcode, INSN_ALIAS },
-{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
+{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_opcode, 0 },
+{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_opcode, 0 },
+{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_opcode, 0 },
+{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_opcode, 0 },
+{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_opcode, 0 },
+{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_opcode, 0 },
{"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
{"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
-{"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
-{"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
-{"vwmulu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
-{"vwmulu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
-{"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
-{"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
+{"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+{"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_vd_neq_vs2_neq_vm, 0 },
+{"vwmulu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+{"vwmulu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_vd_neq_vs2_neq_vm, 0 },
+{"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0 },
+{"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_vd_neq_vs2_neq_vm, 0 },
{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
-{"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vwmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vwmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vwmaccsu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vwmaccsu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vwmaccus.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
+{"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_vd_neq_vs2_neq_vm, 0},
+{"vwmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vwmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_vd_neq_vs2_neq_vm, 0},
+{"vwmaccsu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vwmaccsu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_vd_neq_vs2_neq_vm, 0},
+{"vwmaccus.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_vd_neq_vs2_neq_vm, 0},
{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
-{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
-{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
+{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_opcode, 0 },
+{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_opcode, 0 },
+{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_opcode, 0 },
+{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 },
+{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
+{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },
{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
-{"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vfwsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwadd.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
-{"vfwadd.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
-{"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
-{"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
+{"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_vd_neq_vs2_neq_vm, 0},
+{"vfwsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vfwsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_vd_neq_vs2_neq_vm, 0},
+{"vfwadd.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_vd_neq_vs1_neq_vm, 0},
+{"vfwadd.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_vd_neq_vm, 0},
+{"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_vd_neq_vs1_neq_vm, 0},
+{"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_vd_neq_vm, 0},
{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
-{"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
+{"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_vd_neq_vs2_neq_vm, 0},
{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
-{"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vfwmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
-{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
+{"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_vd_neq_vs2_neq_vm, 0},
+{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_vd_neq_vs2_neq_vm, 0},
+{"vfwmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vfwmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_vd_neq_vs2_neq_vm, 0},
+{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
+{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_vd_neq_vs2_neq_vm, 0},
{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
{"vfrsqrt7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
-{"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
-{"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
-
-{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
-{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
-{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
-{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
-{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
-{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
-{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
-{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
+{"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_vd_neq_vs2_neq_vm, 0},
+{"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_vd_neq_vs2_neq_vm, 0},
+{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_vd_neq_vs2_neq_vm, 0},
+{"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_vd_neq_vs2_neq_vm, 0},
+{"vfwcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_vd_neq_vs2_neq_vm, 0},
+{"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_vd_neq_vs2_neq_vm, 0},
+{"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_vd_neq_vs2_neq_vm, 0},
+
+{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_opcode, 0},
+{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_opcode, 0},
+{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_opcode, 0},
+{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_opcode, 0},
+{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_opcode, 0},
+{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_opcode, 0},
+{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_opcode, 0},
+{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_opcode, 0},
{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
projects / thirdparty / binutils-gdb.git / commitdiff
