RISC-V: Adjust the strided store testcases check times on options

The vsse* dump check times changes on options (O2, O3) after we add
(mem:BLK (scratch)) to the define_insn of strided load.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Adjust
	the vsse check times based on optimization option.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
index e4f6a40873be110ce71f37a2660ef51089b5dca8..2be8854a0b64627f873c83f5da4afdef1c7745bf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(double)
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
 /* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
index afbce2263681b25215409fc80186786e638be198..13003e2ccdcbf1eaa51fe22da2894ffc5bf3a645 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(int64_t)
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
 /* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
index a66eb5bcfd41e477898e94553f917ac8053265a6..5df2caa793b4b14b286dbfd74d190688191db672 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(uint64_t)
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
 /* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } } } } */