EDAC: Use string choice helper functions

Remove hard-coded strings by using the str_enabled_disabled(), str_yes_no(),
str_write_read(), and str_plural() helper functions.

Add a space in "All DIMMs support ECC: yes/no" to improve readability.

Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20250223212429.3466-2-thorsten.blum@linux.dev

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 8414ceb43e4acd1795a6d5c8472cb507cc12f357..d133a5be58905d7dd6560a6ee655027630dc08cd 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 #include <linux/ras.h>
+#include <linux/string_choices.h>
 #include "amd64_edac.h"
 #include <asm/amd_nb.h>
 #include <asm/amd_node.h>
@@ -1171,22 +1172,21 @@ static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
                edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
        }
 
-       edac_dbg(1, "All DIMMs support ECC:%s\n",
-                   (dclr & BIT(19)) ? "yes" : "no");
+       edac_dbg(1, "All DIMMs support ECC: %s\n", str_yes_no(dclr & BIT(19)));
 
 
        edac_dbg(1, "  PAR/ERR parity: %s\n",
-                (dclr & BIT(8)) ?  "enabled" : "disabled");
+                str_enabled_disabled(dclr & BIT(8)));
 
        if (pvt->fam == 0x10)
                edac_dbg(1, "  DCT 128bit mode width: %s\n",
                         (dclr & BIT(11)) ?  "128b" : "64b");
 
        edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
-                (dclr & BIT(12)) ?  "yes" : "no",
-                (dclr & BIT(13)) ?  "yes" : "no",
-                (dclr & BIT(14)) ?  "yes" : "no",
-                (dclr & BIT(15)) ?  "yes" : "no");
+                str_yes_no(dclr & BIT(12)),
+                str_yes_no(dclr & BIT(13)),
+                str_yes_no(dclr & BIT(14)),
+                str_yes_no(dclr & BIT(15)));
 }
 
 #define CS_EVEN_PRIMARY                BIT(0)
@@ -1353,14 +1353,14 @@ static void umc_dump_misc_regs(struct amd64_pvt *pvt)
                edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
 
                edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
-                               i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",
-                                   (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");
+                               i, str_yes_no(umc->umc_cap_hi & BIT(30)),
+                                   str_yes_no(umc->umc_cap_hi & BIT(31)));
                edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",
-                               i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");
+                               i, str_yes_no(umc->umc_cfg & BIT(12)));
                edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",
-                               i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");
+                               i, str_yes_no(umc->dimm_cfg & BIT(6)));
                edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
-                               i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
+                               i, str_yes_no(umc->dimm_cfg & BIT(7)));
 
                umc_debug_display_dimm_sizes(pvt, i);
        }
@@ -1371,11 +1371,11 @@ static void dct_dump_misc_regs(struct amd64_pvt *pvt)
        edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
 
        edac_dbg(1, "  NB two channel DRAM capable: %s\n",
-                (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
+                str_yes_no(pvt->nbcap & NBCAP_DCT_DUAL));
 
        edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",
-                (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
-                (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
+                str_yes_no(pvt->nbcap & NBCAP_SECDED),
+                str_yes_no(pvt->nbcap & NBCAP_CHIPKILL));
 
        debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
 
@@ -1398,7 +1398,7 @@ static void dct_dump_misc_regs(struct amd64_pvt *pvt)
        if (!dct_ganging_enabled(pvt))
                debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
 
-       edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
+       edac_dbg(1, "  DramHoleValid: %s\n", str_yes_no(dhar_valid(pvt)));
 
        amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
 }
@@ -2027,15 +2027,15 @@ static void read_dram_ctl_register(struct amd64_pvt *pvt)
 
                if (!dct_ganging_enabled(pvt))
                        edac_dbg(0, "  Address range split per DCT: %s\n",
-                                (dct_high_range_enabled(pvt) ? "yes" : "no"));
+                                str_yes_no(dct_high_range_enabled(pvt)));
 
                edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
-                        (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
-                        (dct_memory_cleared(pvt) ? "yes" : "no"));
+                        str_enabled_disabled(dct_data_intlv_enabled(pvt)),
+                        str_yes_no(dct_memory_cleared(pvt)));
 
                edac_dbg(0, "  channel interleave: %s, "
                         "interleave bits selector: 0x%x\n",
-                        (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
+                        str_enabled_disabled(dct_interleave_enabled(pvt)),
                         dct_sel_interleave_addr(pvt));
        }
 
@@ -3208,8 +3208,7 @@ static bool nb_mce_bank_enabled_on_node(u16 nid)
                nbe = reg->l & MSR_MCGCTL_NBE;
 
                edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
-                        cpu, reg->q,
-                        (nbe ? "enabled" : "disabled"));
+                        cpu, reg->q, str_enabled_disabled(nbe));
 
                if (!nbe)
                        goto out;
@@ -3353,7 +3352,7 @@ static bool dct_ecc_enabled(struct amd64_pvt *pvt)
                edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
                         MSR_IA32_MCG_CTL, nid);
 
-       edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));
+       edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, str_enabled_disabled(ecc_en));
 
        if (!ecc_en || !nb_mce_en)
                return false;
@@ -3378,7 +3377,7 @@ static bool umc_ecc_enabled(struct amd64_pvt *pvt)
                }
        }
 
-       edac_dbg(3, "Node %d: DRAM ECC %s.\n", pvt->mc_node_id, (ecc_en ? "enabled" : "disabled"));
+       edac_dbg(3, "Node %d: DRAM ECC %s.\n", pvt->mc_node_id, str_enabled_disabled(ecc_en));
 
        return ecc_en;
 }

diff --git a/drivers/edac/debugfs.c b/drivers/edac/debugfs.c
index 4804332d99465e8242c2c8a8f1d014c53e93ebfd..8195fc9c9354a3664adfabfb040eee44e25ca9a1 100644 (file)
--- a/drivers/edac/debugfs.c
+++ b/drivers/edac/debugfs.c
@@ -1,4 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/string_choices.h>
+
 #include "edac_module.h"
 
 static struct dentry *edac_debugfs;
@@ -22,7 +25,7 @@ static ssize_t edac_fake_inject_write(struct file *file,
               "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
                errcount,
                (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
-               errcount > 1 ? "s" : "",
+               str_plural(errcount),
                mci->fake_inject_layer[0],
                mci->fake_inject_layer[1],
                mci->fake_inject_layer[2]

diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c
index 49b4499269fb75f9f45a5c448227a721e5feccee..b5cf25905b059d4273aae0795feda886a45d3cf8 100644 (file)
--- a/drivers/edac/i5400_edac.c
+++ b/drivers/edac/i5400_edac.c
@@ -31,6 +31,7 @@
 #include <linux/slab.h>
 #include <linux/edac.h>
 #include <linux/mmzone.h>
+#include <linux/string_choices.h>
 
 #include "edac_module.h"
 
@@ -899,7 +900,7 @@ static void decode_mtr(int slot_row, u16 mtr)
        edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
 
        edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
-                MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
+                str_enabled_disabled(MTR_DIMMS_ETHROTTLE(mtr)));
 
        edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
        edac_dbg(2, "\t\tNUMRANK: %s\n",

diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index 61adaa872ba7bba8c15be82c658455c95bff1c2f..69068f8d0cadfb08c73c96ede8868c74e66c8ec8 100644 (file)
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -23,6 +23,7 @@
 #include <linux/slab.h>
 #include <linux/edac.h>
 #include <linux/mmzone.h>
+#include <linux/string_choices.h>
 
 #include "edac_module.h"
 
@@ -620,7 +621,7 @@ static int decode_mtr(struct i7300_pvt *pvt,
        edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
 
        edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
-                MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
+                str_enabled_disabled(MTR_DIMMS_ETHROTTLE(mtr)));
 
        edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
        edac_dbg(2, "\t\tNUMRANK: %s\n",
@@ -871,9 +872,9 @@ static int i7300_get_mc_regs(struct mem_ctl_info *mci)
                         IS_MIRRORED(pvt->mc_settings) ? "" : "non-");
 
        edac_dbg(0, "Error detection is %s\n",
-                IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
+                str_enabled_disabled(IS_ECC_ENABLED(pvt->mc_settings)));
        edac_dbg(0, "Retry is %s\n",
-                IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
+                str_enabled_disabled(IS_RETRY_ENABLED(pvt->mc_settings)));
 
        /* Get Memory Interleave Range registers */
        pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,

diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c
index 699c7d29d80cd63b0187dee8af3da010d9b7a7a4..9955396c9a5206e83aed777bcba5741f9009c41b 100644 (file)
--- a/drivers/edac/xgene_edac.c
+++ b/drivers/edac/xgene_edac.c
@@ -15,6 +15,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/regmap.h>
+#include <linux/string_choices.h>
 
 #include "edac_module.h"
 
@@ -1407,7 +1408,7 @@ static void xgene_edac_iob_gic_report(struct edac_device_ctl_info *edac_dev)
                dev_err(edac_dev->dev, "Multiple XGIC write size error\n");
        info = readl(ctx->dev_csr + XGICTRANSERRREQINFO);
        dev_err(edac_dev->dev, "XGIC %s access @ 0x%08X (0x%08X)\n",
-               info & REQTYPE_MASK ? "read" : "write", ERRADDR_RD(info),
+               str_read_write(info & REQTYPE_MASK), ERRADDR_RD(info),
                info);
        writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS);
 
@@ -1489,19 +1490,19 @@ static void xgene_edac_rb_report(struct edac_device_ctl_info *edac_dev)
                if (reg & AGENT_OFFLINE_ERR_MASK)
                        dev_err(edac_dev->dev,
                                "IOB bus %s access to offline agent error\n",
-                               write ? "write" : "read");
+                               str_write_read(write));
                if (reg & UNIMPL_RBPAGE_ERR_MASK)
                        dev_err(edac_dev->dev,
                                "IOB bus %s access to unimplemented page error\n",
-                               write ? "write" : "read");
+                               str_write_read(write));
                if (reg & WORD_ALIGNED_ERR_MASK)
                        dev_err(edac_dev->dev,
                                "IOB bus %s word aligned access error\n",
-                               write ? "write" : "read");
+                               str_write_read(write));
                if (reg & PAGE_ACCESS_ERR_MASK)
                        dev_err(edac_dev->dev,
                                "IOB bus %s to page out of range access error\n",
-                               write ? "write" : "read");
+                               str_write_read(write));
                if (regmap_write(ctx->edac->rb_map, RBEIR, 0))
                        return;
                if (regmap_write(ctx->edac->rb_map, RBCSR, 0))
@@ -1560,7 +1561,7 @@ rb_skip:
        err_addr_lo = readl(ctx->dev_csr + IOBBATRANSERRREQINFOL);
        err_addr_hi = readl(ctx->dev_csr + IOBBATRANSERRREQINFOH);
        dev_err(edac_dev->dev, "IOB BA %s access at 0x%02X.%08X (0x%08X)\n",
-               REQTYPE_F2_RD(err_addr_hi) ? "read" : "write",
+               str_read_write(REQTYPE_F2_RD(err_addr_hi)),
                ERRADDRH_F2_RD(err_addr_hi), err_addr_lo, err_addr_hi);
        if (reg & WRERR_RESP_MASK)
                dev_err(edac_dev->dev, "IOB BA requestor ID 0x%08X\n",
@@ -1611,7 +1612,7 @@ chk_iob_axi0:
        dev_err(edac_dev->dev,
                "%sAXI slave 0 illegal %s access @ 0x%02X.%08X (0x%08X)\n",
                reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "",
-               REQTYPE_RD(err_addr_hi) ? "read" : "write",
+               str_read_write(REQTYPE_RD(err_addr_hi)),
                ERRADDRH_RD(err_addr_hi), err_addr_lo, err_addr_hi);
        writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
 
@@ -1625,7 +1626,7 @@ chk_iob_axi1:
        dev_err(edac_dev->dev,
                "%sAXI slave 1 illegal %s access @ 0x%02X.%08X (0x%08X)\n",
                reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "",
-               REQTYPE_RD(err_addr_hi) ? "read" : "write",
+               str_read_write(REQTYPE_RD(err_addr_hi)),
                ERRADDRH_RD(err_addr_hi), err_addr_lo, err_addr_hi);
        writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
 }