Arm: Backport hlt to all architectures.

The software trap instruction HLT that was introduced in Armv8-a is used
as the semihosting trap instruction in AArch64.  In order to allow systems
configured to run AArch64 code to also run AArch32 with semihosting it was
decided that AArch32 should also use HLT in the case of the "mixed mode"
environment.  This requires that HLT also be backported to all earlier
architectures.  The instruction is in the undefined encoding space earlier
architectures but must trigger a semihosting trap [3].

The Arm Architectural Reference Manual [1] doesn't explicitly mention this
however this is an explicit requirement in the Semihosting-v2 protocol [2].

[1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
[3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e

gas/ChangeLog:

	* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
	hlt to armv1.
	* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
	* testsuite/gas/arm/hlt.d: New test.
	* testsuite/gas/arm/hlt.s: New test.

opcodes/ChangeLog:

	* arm-dis.c (arm_opcodes): Redefine hlt to armv1.

(cherry picked from commit f7dd2fb2e2b750f0fb9dedaf885c17bc6beef1f7)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6ec14ac687d06f57dc618872efd284ca03567093..550cbedf86ffab52145d9687c6d3911ca6bf713e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2019-02-07  Tamar Christina  <tamar.christina@arm.com>
+
+       * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
+       hlt to armv1.
+       * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
+       * testsuite/gas/arm/hlt.d: New test.
+       * testsuite/gas/arm/hlt.s: New test.
+
 2019-02-07  Eric Botcazou  <ebotcazou@adacore.com>
 
        * config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 81b5ceedcc9dba5a8d0309731f03108e3853d3d8..e6600f6b10e6edee7c28cbebffff540326071578 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -20187,11 +20187,22 @@ static const struct asm_opcode insns[] =
 #define THUMB_VARIANT & arm_ext_v8
 
  tCE("sevl",   320f005, _sevl,    0, (),               noargs, t_hint),
- TUE("hlt",    1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
  TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
                                                        ldrexd, t_ldrexd),
  TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
                                                        strexd, t_strexd),
+
+/* Defined in V8 but is in undefined encoding space for earlier
+   architectures.  However earlier architectures are required to treat
+   this instuction as a semihosting trap as well.  Hence while not explicitly
+   defined as such, it is in fact correct to define the instruction for all
+   architectures.  */
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_v1
+#undef  ARM_VARIANT
+#define ARM_VARIANT  & arm_ext_v1
+ TUE("hlt",    1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
+
  /* ARMv8 T32 only.  */
 #undef  ARM_VARIANT
 #define ARM_VARIANT  NULL

diff --git a/gas/testsuite/gas/arm/armv8a-automatic-hlt.d b/gas/testsuite/gas/arm/armv8a-automatic-hlt.d
index ee6c428538f8616f2d0a48f3e2ed35b0f6d8a002..9ce94d36c92d8cd1d9daa50088a1d9fb9f4ddccd 100644 (file)
--- a/gas/testsuite/gas/arm/armv8a-automatic-hlt.d
+++ b/gas/testsuite/gas/arm/armv8a-automatic-hlt.d
@@ -5,4 +5,6 @@ Attribute Section: aeabi
 File Attributes
   Tag_CPU_arch: v8
   Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
   Tag_THUMB_ISA_use: Thumb-2
+

diff --git a/gas/testsuite/gas/arm/hlt.d b/gas/testsuite/gas/arm/hlt.d
new file mode 100644 (file)
index 0000000..b05c1fb
--- /dev/null
+++ b/gas/testsuite/gas/arm/hlt.d
@@ -0,0 +1,35 @@
+#objdump: -d
+# This test is only valid on ELF based ports.
+#notarget: *-*-pe *-*-wince
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:\s+ba80          hlt     0x0000
+[^:]+:\s+ba8f          hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f
+[^:]+:\s+ba80          hlt     0x0000
+[^:]+:\s+ba8f          hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f
+[^:]+:\s+ba80          hlt     0x0000
+[^:]+:\s+ba8f          hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f
+[^:]+:\s+ba80          hlt     0x0000
+[^:]+:\s+ba8f          hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f
+[^:]+:\s+ba80          hlt     0x0000
+[^:]+:\s+ba8f          hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f
+[^:]+:\s+e1000070      hlt     0x0000
+[^:]+:\s+e100007f      hlt     0x000f

diff --git a/gas/testsuite/gas/arm/hlt.s b/gas/testsuite/gas/arm/hlt.s
new file mode 100644 (file)
index 0000000..02d1316
--- /dev/null
+++ b/gas/testsuite/gas/arm/hlt.s
@@ -0,0 +1,22 @@
+# Test that hlt is available for all architectures.
+.macro gen_for_arch arch, has_thumb
+       .arch \arch
+       .ifc "yes","\has_thumb"
+       .thumb
+       hlt
+       hlt 0xf
+       .endif
+       .arm
+       hlt
+       hlt 0xf
+.endm
+
+gen_for_arch armv8-a, yes
+gen_for_arch armv7-a, yes
+gen_for_arch armv6, yes
+gen_for_arch armv5t, yes
+gen_for_arch armv4t, yes
+gen_for_arch armv3, no
+gen_for_arch armv2, no
+gen_for_arch armv1, no
+

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fc3ec349402968e23fae40ec72ac5f03a64a6d94..fa310a7582d9aed6bf21e90bd494acebfa6b2754 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2019-02-07  Tamar Christina  <tamar.christina@arm.com>
+
+       * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
+
 2019-02-07  Nick Clifton  <nickc@redhat.com>
 
        * po/sv.po: Updated Swedish translation.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 488522770f8a6b5932cb68f3cd64c1a3c63db3f2..71d7c524a22b0d93e5b0dd1573abbe158cd636e8 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1788,7 +1788,8 @@ static const struct opcode32 arm_opcodes[] =
   /* V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0x0320f005, 0x0fffffff, "sevl"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  /* Defined in V8 but is in NOP space so available to all arch.  */
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},