drm/amd/display: Remove check DPIA HPD status for BW Allocation

[Why & How]
Link hpd_status is for embedded DPIA only.
Do not check hpd_status for BW allocation logic.

Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index aecaf37eee3520d8b30edbfb5b575df510a5b4a0..acdc162de5353bc119721ecafcb97c3a1c2a7573 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -408,8 +408,10 @@ enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const stru
                link = stream->link;
 
                if (!(link && (stream->signal == SIGNAL_TYPE_DISPLAY_PORT
-                               || stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-                               && link->hpd_status))
+                               || stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)))
+                       continue;
+
+               if ((link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) && (link->hpd_status == false))
                        continue;
 
                dp_tunnel_settings = get_dp_tunnel_settings(new_ctx, stream);

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index 819bf2d8ba530bec22f7ab5a954de0d04d95bbfc..906d85ca89569c74e1772d6953b6e800d4f3911c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -48,8 +48,7 @@
  */
 static bool link_dp_is_bw_alloc_available(struct dc_link *link)
 {
-       return (link && link->hpd_status
-               && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
+       return (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
                && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
                && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);
 }
@@ -226,35 +225,35 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link)
        bool ret = false;
        uint8_t val;
 
-       if (link->hpd_status) {
-               val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;
+       val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;
 
-               if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {
-                       DC_LOG_DEBUG("%s:  link[%d] DPTX BW allocation mode enabled", __func__, link->link_index);
+       if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {
+               DC_LOG_DEBUG("%s:  link[%d] DPTX BW allocation mode enabled", __func__, link->link_index);
 
-                       retrieve_usb4_dp_bw_allocation_info(link);
+               retrieve_usb4_dp_bw_allocation_info(link);
 
-                       if (link->dpia_bw_alloc_config.nrd_max_link_rate && link->dpia_bw_alloc_config.nrd_max_lane_count) {
-                               link->reported_link_cap.link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate;
-                               link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count;
-                       }
+               if (
+                               link->dpia_bw_alloc_config.nrd_max_link_rate
+                               && link->dpia_bw_alloc_config.nrd_max_lane_count) {
+                       link->reported_link_cap.link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate;
+                       link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count;
+               }
 
-                       link->dpia_bw_alloc_config.bw_alloc_enabled = true;
-                       ret = true;
-
-                       if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) {
-                               /*
-                                * During DP tunnel creation, the CM preallocates BW
-                                * and reduces the estimated BW of other DPIAs.
-                                * The CM releases the preallocation only when the allocation is complete.
-                                * Perform a zero allocation to make the CM release the preallocation
-                                * and correctly update the estimated BW for all DPIAs per host router.
-                                */
-                               link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0);
-                       }
-               } else
-                       DC_LOG_DEBUG("%s:  link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index);
-       }
+               link->dpia_bw_alloc_config.bw_alloc_enabled = true;
+               ret = true;
+
+               if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) {
+                       /*
+                        * During DP tunnel creation, the CM preallocates BW
+                        * and reduces the estimated BW of other DPIAs.
+                        * The CM releases the preallocation only when the allocation is complete.
+                        * Perform a zero allocation to make the CM release the preallocation
+                        * and correctly update the estimated BW for all DPIAs per host router.
+                        */
+                       link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0);
+               }
+       } else
+               DC_LOG_DEBUG("%s:  link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index);
 
        return ret;
 }
@@ -297,15 +296,12 @@ void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pe
 {
        if (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
                        && link->dpia_bw_alloc_config.bw_alloc_enabled) {
-               //1. Hot Plug
-               if (link->hpd_status && peak_bw > 0) {
+               if (peak_bw > 0) {
                        // If DP over USB4 then we need to check BW allocation
                        link->dpia_bw_alloc_config.link_max_bw = peak_bw;
 
                        link_dpia_send_bw_alloc_request(link, peak_bw);
-               }
-               //2. Cold Unplug
-               else if (!link->hpd_status)
+               } else
                        dpia_bw_alloc_unplug(link);
        }
 }