drm/xe: Check for primary GT before looking up Wa_22019338487

If the primary GT is disabled via configfs, we need to make sure that we
don't search for this workaround on a NULL xe_gt pointer.  Since we can
disable the primary GT only on igpu platforms, the media GT is the one
we'd want to check anyway for this workaround.

The ternary operators in ggtt_update_access_counter() were getting a bit
long/complicated, so rewrite them with regular if/else statements.
While we're at it, throw in a couple extra assertions to make sure that
we're truly picking the expected GT according to igpu/dgpu type.

v2:
 - Adjust indentation/wrapping; it's easier to read this with longer,
   unwrapped lines.  (Lucas)
 - Tweak wording of commit message to remove ambiguity.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20251013200944.2499947-37-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index aca7ae5489b91b81f7c3ad4415a0533449c72e07..40680f0c49a1781034c0f0cecadd08efb884991c 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -107,10 +107,23 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
 static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
 {
        struct xe_tile *tile = ggtt->tile;
-       struct xe_gt *affected_gt = XE_GT_WA(tile->primary_gt, 22019338487) ?
-               tile->primary_gt : tile->media_gt;
-       struct xe_mmio *mmio = &affected_gt->mmio;
-       u32 max_gtt_writes = XE_GT_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;
+       struct xe_gt *affected_gt;
+       u32 max_gtt_writes;
+
+       if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) {
+               affected_gt = tile->primary_gt;
+               max_gtt_writes = 1100;
+
+               /* Only expected to apply to primary GT on dgpu platforms */
+               xe_tile_assert(tile, IS_DGFX(tile_to_xe(tile)));
+       } else {
+               affected_gt = tile->media_gt;
+               max_gtt_writes = 63;
+
+               /* Only expected to apply to media GT on igpu platforms */
+               xe_tile_assert(tile, !IS_DGFX(tile_to_xe(tile)));
+       }
+
        /*
         * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
         * to wait for completion of prior GTT writes before letting this through.
@@ -119,7 +132,7 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
        lockdep_assert_held(&ggtt->lock);
 
        if ((++ggtt->access_count % max_gtt_writes) == 0) {
-               xe_mmio_write32(mmio, GMD_ID, 0x0);
+               xe_mmio_write32(&affected_gt->mmio, GMD_ID, 0x0);
                ggtt->access_count = 0;
        }
 }
@@ -291,10 +304,10 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
                ggtt->size = GUC_GGTT_TOP;
 
        if (GRAPHICS_VERx100(xe) >= 1270)
-               ggtt->pt_ops = (ggtt->tile->media_gt &&
-                              XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
-                              XE_GT_WA(ggtt->tile->primary_gt, 22019338487) ?
-                              &xelpg_pt_wa_ops : &xelpg_pt_ops;
+               ggtt->pt_ops =
+                       (ggtt->tile->media_gt && XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
+                       (ggtt->tile->primary_gt && XE_GT_WA(ggtt->tile->primary_gt, 22019338487)) ?
+                       &xelpg_pt_wa_ops : &xelpg_pt_ops;
        else
                ggtt->pt_ops = &xelp_pt_ops;