arm.h (CLASS_LIKELY_SPILLED_P): Remove.

	* config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Remove.
	* config/arm/arm.c (TARGET_CLASS_LIKELY_SPILLED_P): Define.
	(arm_class_likely_spilled_p): New function.

From-SVN: r164450

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 88f350e1269215376092c67b1d04441655cc4e9c..4e6b97cf33dcc683dea4bba613958baf13caa96d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2010-09-20  Anatoly Sokolov  <aesok@post.ru>
+
+       * config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Remove.
+       * config/arm/arm.c (TARGET_CLASS_LIKELY_SPILLED_P): Define.
+       (arm_class_likely_spilled_p): New function.
+
 2010-09-20  Uros Bizjak  <ubizjak@gmail.com>
 
        * config/i386/i386.c (ix86_expand_ashl_const): Rewrite using

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7cb3186dc014e3303ac3786523518eb3a2907243..0701b487cac1dd7698166635eda6b4736ffee415 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -239,6 +239,7 @@ static rtx arm_pic_static_addr (rtx orig, rtx reg);
 static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
 static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
 static unsigned int arm_units_per_simd_word (enum machine_mode);
+static bool arm_class_likely_spilled_p (reg_class_t);
 
 \f
 /* Table of machine attributes.  */
@@ -545,6 +546,9 @@ static const struct attribute_spec arm_attribute_table[] =
 #undef TARGET_CAN_ELIMINATE
 #define TARGET_CAN_ELIMINATE arm_can_eliminate
 
+#undef TARGET_CLASS_LIKELY_SPILLED_P
+#define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 \f
 /* Obstack for minipool constant handling.  */
@@ -21952,6 +21956,22 @@ arm_units_per_simd_word (enum machine_mode mode ATTRIBUTE_UNUSED)
          ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD);
 }
 
+/* Implement TARGET_CLASS_LIKELY_SPILLED_P.
+ 
+   We need to define this for LO_REGS on thumb.  Otherwise we can end up
+   using r0-r4 for function arguments, r7 for the stack frame and don't
+   have enough left over to do doubleword arithmetic.  */
+
+static bool
+arm_class_likely_spilled_p (reg_class_t rclass)
+{
+  if ((TARGET_THUMB && rclass == LO_REGS)
+      || rclass  == CC_REG)
+    return true;
+
+  return false;
+}
+
 /* Implements target hook small_register_classes_for_mode_p.  */
 bool
 arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8727305a6e21ff6c511df612918efb711a4c67fb..2252a2512b1afdcdbaa77ee28ef8e9b8904cdf81 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1284,13 +1284,6 @@ enum reg_class
      || reg_classes_intersect_p (VFP_REGS, (CLASS))    \
    : 0)
 
-/* We need to define this for LO_REGS on thumb.  Otherwise we can end up
-   using r0-r4 for function arguments, r7 for the stack frame and don't
-   have enough left over to do doubleword arithmetic.  */
-#define CLASS_LIKELY_SPILLED_P(CLASS)  \
-    ((TARGET_THUMB && (CLASS) == LO_REGS)      \
-     || (CLASS) == CC_REG)
-
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS  (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
 #define BASE_REG_CLASS   (TARGET_THUMB1 ? LO_REGS : CORE_REGS)