ARM: dts: imx6sl: align pin config nodes with bindings

Bindings for other NXP pin controllers expect pin configuration nodes in
pinctrl to match certain naming, so adjust these as well, even though
their bindings are not yet in dtschema format.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts
index 31eee0419af71c628c1b2849fa944e30df891af8..7c899291ab0dada4bdf0ed2b7a4829bc09523fae 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts
@@ -457,7 +457,7 @@
                        >;
                };
 
-               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+               pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD1_CMD__SD1_CMD              0x170b9
                                MX6SL_PAD_SD1_CLK__SD1_CLK              0x100b9
@@ -472,7 +472,7 @@
                        >;
                };
 
-               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+               pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD1_CMD__SD1_CMD              0x170f9
                                MX6SL_PAD_SD1_CLK__SD1_CLK              0x100f9
@@ -498,7 +498,7 @@
                        >;
                };
 
-               pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+               pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x170b9
                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x100b9
@@ -509,7 +509,7 @@
                        >;
                };
 
-               pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+               pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x170f9
                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x100f9
@@ -531,7 +531,7 @@
                        >;
                };
 
-               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+               pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x170b9
                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x100b9
@@ -542,7 +542,7 @@
                        >;
                };
 
-               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+               pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x170f9
                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x100f9

diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts
index 9d7c8884892a9b39d4db7fb1e900e16efb6fa32e..2545c0fe47c82851807d36427e6a10e12af48b27 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts
@@ -166,7 +166,7 @@
                        >;
                };
 
-               pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+               pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170b9
                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100b9
@@ -182,7 +182,7 @@
                        >;
                };
 
-               pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+               pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170f9
                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100f9
@@ -209,7 +209,7 @@
                        >;
                };
 
-               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+               pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170b9
                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100b9
@@ -220,7 +220,7 @@
                        >;
                };
 
-               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+               pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
                        fsl,pins = <
                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170f9
                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100f9