--- /dev/null
+From 3b25eb690e8c7424eecffe1458c02b87b32aa001 Mon Sep 17 00:00:00 2001
+From: Takashi Iwai <tiwai@suse.de>
+Date: Wed, 25 Jan 2012 09:55:46 +0100
+Subject: ALSA: hda - Fix silent output on ASUS A6Rp
+
+From: Takashi Iwai <tiwai@suse.de>
+
+commit 3b25eb690e8c7424eecffe1458c02b87b32aa001 upstream.
+
+The refactoring of Realtek codec driver in 3.2 kernel caused a
+regression for ASUS A6Rp laptop; it doesn't give any output.
+The reason was that this machine has a secret master mute (or EAPD)
+control via NID 0x0f VREF. Setting VREF50 on this node makes the
+sound working again.
+
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=42588
+
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ sound/pci/hda/patch_realtek.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -5223,6 +5223,7 @@ static const struct hda_amp_list alc861_
+ /* Pin config fixes */
+ enum {
+ PINFIX_FSC_AMILO_PI1505,
++ PINFIX_ASUS_A6RP,
+ };
+
+ static const struct alc_fixup alc861_fixups[] = {
+@@ -5234,9 +5235,18 @@ static const struct alc_fixup alc861_fix
+ { }
+ }
+ },
++ [PINFIX_ASUS_A6RP] = {
++ .type = ALC_FIXUP_VERBS,
++ .v.verbs = (const struct hda_verb[]) {
++ /* node 0x0f VREF seems controlling the master output */
++ { 0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF50 },
++ { }
++ },
++ },
+ };
+
+ static const struct snd_pci_quirk alc861_fixup_tbl[] = {
++ SND_PCI_QUIRK(0x1043, 0x1393, "ASUS A6Rp", PINFIX_ASUS_A6RP),
+ SND_PCI_QUIRK(0x1734, 0x10c7, "FSC Amilo Pi1505", PINFIX_FSC_AMILO_PI1505),
+ {}
+ };
--- /dev/null
+From b3a81520bd37a28f77cb0f7002086fb14061824d Mon Sep 17 00:00:00 2001
+From: Takashi Iwai <tiwai@suse.de>
+Date: Thu, 26 Jan 2012 15:56:16 +0100
+Subject: ALSA: hda - Fix silent output on Haier W18 laptop
+
+From: Takashi Iwai <tiwai@suse.de>
+
+commit b3a81520bd37a28f77cb0f7002086fb14061824d upstream.
+
+The very same problem is seen on Haier W18 laptop with ALC861 as seen
+on ASUS A6Rp, which was fixed by the commit 3b25eb69.
+Now we just need to add a new SSID entry pointing to the same fixup.
+
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=42656
+
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ sound/pci/hda/patch_realtek.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -5247,6 +5247,7 @@ static const struct alc_fixup alc861_fix
+
+ static const struct snd_pci_quirk alc861_fixup_tbl[] = {
+ SND_PCI_QUIRK(0x1043, 0x1393, "ASUS A6Rp", PINFIX_ASUS_A6RP),
++ SND_PCI_QUIRK(0x1584, 0x2b01, "Haier W18", PINFIX_ASUS_A6RP),
+ SND_PCI_QUIRK(0x1734, 0x10c7, "FSC Amilo Pi1505", PINFIX_FSC_AMILO_PI1505),
+ {}
+ };
--- /dev/null
+From a6a600d10aaddf1da38053c4c6b64f50f56176e6 Mon Sep 17 00:00:00 2001
+From: Gustavo Maciel Dias Vieira <gustavo@sagui.org>
+Date: Tue, 24 Jan 2012 13:27:56 -0200
+Subject: ALSA: hda: set mute led polarity for laptops with buggy BIOS based on SSID
+
+From: Gustavo Maciel Dias Vieira <gustavo@sagui.org>
+
+commit a6a600d10aaddf1da38053c4c6b64f50f56176e6 upstream.
+
+HP laptop models with buggy BIOS are apparently frequent, including
+machines with different codecs. Set the polarity of the mute led based
+on the SSID and include an entry for the HP Mini 110-3100.
+
+Signed-off-by: Gustavo Maciel Dias Vieira <gustavo@sagui.org>
+Tested-by: Predrag Ivanovic <predivan@open.telekom.rs>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ sound/pci/hda/patch_sigmatel.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/sound/pci/hda/patch_sigmatel.c
++++ b/sound/pci/hda/patch_sigmatel.c
+@@ -4952,7 +4952,14 @@ static int find_mute_led_gpio(struct hda
+ /* BIOS bug: unfilled OEM string */
+ if (strstr(dev->name, "HP_Mute_LED_P_G")) {
+ set_hp_led_gpio(codec);
+- spec->gpio_led_polarity = 1;
++ switch (codec->subsystem_id) {
++ case 0x103c148a:
++ spec->gpio_led_polarity = 0;
++ break;
++ default:
++ spec->gpio_led_polarity = 1;
++ break;
++ }
+ return 1;
+ }
+ }
--- /dev/null
+From 4cd53c0c8b01fc05c3ad5b2acdad02e37d3c2f55 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Fri, 14 Dec 2012 16:01:25 +0100
+Subject: drm/i915: paper over missed irq issues with force wake voodoo
+
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 4cd53c0c8b01fc05c3ad5b2acdad02e37d3c2f55 upstream.
+
+Two things seem to do the trick on my ivb machine here:
+- prevent the gt from powering down while waiting for seqno
+ notification interrupts by grabbing the force_wake in get_irq (and
+ dropping it in put_irq again).
+- ordering writes from the ring's CS by reading a CS register, ACTHD
+ seems to work.
+
+Only the blt&bsd ring on ivb seem to be massively affected by this,
+but for paranoia do this dance also on the render ring and on snb
+(i.e. all gpus with forcewake).
+
+Tested with Eric's glCopyPixels loop which without this patch scores a
+missed irq every few seconds.
+
+This patch needs my forcewake rework to use a spinlock instead of
+dev->struct_mutex.
+
+After crawling through docs a lot I've found the following nugget:
+
+Internal doc "SNB GT PM Programming Guide", Section 4.3.1:
+
+"GT does not generate interrupts while in RC6 (by design)"
+
+So it looks like rc6 and irq generation are indeed related.
+
+v2: Improve the comment per Eugeni Dodonov's suggestion.
+
+v3: Add the documentation snipped. Also restrict the w/a to ivb only
+for -fixes, as suggested by Keith Packard.
+
+Cc: Eric Anholt <eric@anholt.net>
+Cc: Kenneth Graunke <kenneth@whitecape.org>
+Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
+Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
+Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
+Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Keith Packard <keithp@keithp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_ringbuffer.c | 27 +++++++++++++++++++++++++--
+ 1 file changed, 25 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
+@@ -631,6 +631,19 @@ render_ring_add_request(struct intel_rin
+ }
+
+ static u32
++gen6_ring_get_seqno(struct intel_ring_buffer *ring)
++{
++ struct drm_device *dev = ring->dev;
++
++ /* Workaround to force correct ordering between irq and seqno writes on
++ * ivb (and maybe also on snb) by reading from a CS register (like
++ * ACTHD) before reading the status page. */
++ if (IS_GEN7(dev))
++ intel_ring_get_active_head(ring);
++ return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
++}
++
++static u32
+ ring_get_seqno(struct intel_ring_buffer *ring)
+ {
+ return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
+@@ -795,6 +808,12 @@ gen6_ring_get_irq(struct intel_ring_buff
+ if (!dev->irq_enabled)
+ return false;
+
++ /* It looks like we need to prevent the gt from suspending while waiting
++ * for an notifiy irq, otherwise irqs seem to get lost on at least the
++ * blt/bsd rings on ivb. */
++ if (IS_GEN7(dev))
++ gen6_gt_force_wake_get(dev_priv);
++
+ spin_lock(&ring->irq_lock);
+ if (ring->irq_refcount++ == 0) {
+ ring->irq_mask &= ~rflag;
+@@ -819,6 +838,9 @@ gen6_ring_put_irq(struct intel_ring_buff
+ ironlake_disable_irq(dev_priv, gflag);
+ }
+ spin_unlock(&ring->irq_lock);
++
++ if (IS_GEN7(dev))
++ gen6_gt_force_wake_put(dev_priv);
+ }
+
+ static bool
+@@ -1316,7 +1338,7 @@ static const struct intel_ring_buffer ge
+ .write_tail = gen6_bsd_ring_write_tail,
+ .flush = gen6_ring_flush,
+ .add_request = gen6_add_request,
+- .get_seqno = ring_get_seqno,
++ .get_seqno = gen6_ring_get_seqno,
+ .irq_get = gen6_bsd_ring_get_irq,
+ .irq_put = gen6_bsd_ring_put_irq,
+ .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
+@@ -1451,7 +1473,7 @@ static const struct intel_ring_buffer ge
+ .write_tail = ring_write_tail,
+ .flush = blt_ring_flush,
+ .add_request = gen6_add_request,
+- .get_seqno = ring_get_seqno,
++ .get_seqno = gen6_ring_get_seqno,
+ .irq_get = blt_ring_get_irq,
+ .irq_put = blt_ring_put_irq,
+ .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
+@@ -1474,6 +1496,7 @@ int intel_init_render_ring_buffer(struct
+ ring->flush = gen6_render_ring_flush;
+ ring->irq_get = gen6_render_ring_get_irq;
+ ring->irq_put = gen6_render_ring_put_irq;
++ ring->get_seqno = gen6_ring_get_seqno;
+ } else if (IS_GEN5(dev)) {
+ ring->add_request = pc_render_add_request;
+ ring->get_seqno = pc_render_get_seqno;
--- /dev/null
+From 04115a9dee110b52a8eaa556c574022fa3bf4704 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 23 Jan 2012 16:14:06 -0800
+Subject: drm/i915: Re-enable gen7 RC6 and GPU turbo after resume.
+
+From: Eric Anholt <eric@anholt.net>
+
+commit 04115a9dee110b52a8eaa556c574022fa3bf4704 upstream.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Keith Packard <keithp@keithp.com>
+Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
+Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+Signed-off-by: Keith Packard <keithp@keithp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_suspend.c
++++ b/drivers/gpu/drm/i915/i915_suspend.c
+@@ -822,7 +822,7 @@ int i915_save_state(struct drm_device *d
+
+ if (IS_IRONLAKE_M(dev))
+ ironlake_disable_drps(dev);
+- if (IS_GEN6(dev))
++ if (INTEL_INFO(dev)->gen >= 6)
+ gen6_disable_rps(dev);
+
+ /* Cache mode state */
+@@ -881,7 +881,7 @@ int i915_restore_state(struct drm_device
+ intel_init_emon(dev);
+ }
+
+- if (IS_GEN6(dev)) {
++ if (INTEL_INFO(dev)->gen >= 6) {
+ gen6_enable_rps(dev_priv);
+ gen6_update_ring_freq(dev_priv);
+ }
--- /dev/null
+From ba68e086223a5f149f37bf8692c8cdbf1b0ba3ef Mon Sep 17 00:00:00 2001
+From: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Date: Fri, 6 Jan 2012 19:45:34 -0200
+Subject: drm/i915/sdvo: always set positive sync polarity
+
+From: Paulo Zanoni <paulo.r.zanoni@intel.com>
+
+commit ba68e086223a5f149f37bf8692c8cdbf1b0ba3ef upstream.
+
+This is a revert of 81a14b46846fea0741902e8d8dfcc6c6c78154c8.
+
+We already set the mode polarity using the SDVO commands with struct
+intel_sdvo_dtd. We have at least 3 bugs that get fixed with this patch.
+The documentation, despite not clear, can also be interpreted in a way
+that suggests this patch is needed.
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15766
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42174
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43333
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
+Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Signed-off-by: Keith Packard <keithp@keithp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_sdvo.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_sdvo.c
++++ b/drivers/gpu/drm/i915/intel_sdvo.c
+@@ -1066,15 +1066,13 @@ static void intel_sdvo_mode_set(struct d
+
+ /* Set the SDVO control regs. */
+ if (INTEL_INFO(dev)->gen >= 4) {
+- sdvox = 0;
++ /* The real mode polarity is set by the SDVO commands, using
++ * struct intel_sdvo_dtd. */
++ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
+ if (intel_sdvo->is_hdmi)
+ sdvox |= intel_sdvo->color_range;
+ if (INTEL_INFO(dev)->gen < 5)
+ sdvox |= SDVO_BORDER_ENABLE;
+- if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+- sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
+- if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+- sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
+ } else {
+ sdvox = I915_READ(intel_sdvo->sdvo_reg);
+ switch (intel_sdvo->sdvo_reg) {
x86-uv-fix-uv_gpa_to_soc_phys_ram-shift.patch
x86-microcode_amd-add-support-for-cpu-family-specific-container-files.patch
m68k-fix-assembler-constraint-to-prevent-overeager-gcc-optimisation.patch
+alsa-hda-set-mute-led-polarity-for-laptops-with-buggy-bios-based-on-ssid.patch
+alsa-hda-fix-silent-output-on-asus-a6rp.patch
+alsa-hda-fix-silent-output-on-haier-w18-laptop.patch
+drm-i915-paper-over-missed-irq-issues-with-force-wake-voodoo.patch
+drm-i915-sdvo-always-set-positive-sync-polarity.patch
+drm-i915-re-enable-gen7-rc6-and-gpu-turbo-after-resume.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
