drm/amd/display: replace dio encoder access

[WHY]
replace dio encoder access to work with new dio encoder
assignment.

[HOW}
1. before validation, access dio encoder by get_temp_dio_link_enc()
2. after validation, access dio encoder through pipe_ctx->link_res

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7eb91612b60d1e9d6bf0d3e004451e6e7e85cb75..0bd3e7c072a1276b42c5823cb924462191568605 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -5191,7 +5191,7 @@ void get_audio_check(struct audio_info *aud_modes,
        }
 }
 
-static struct link_encoder *get_temp_dio_link_enc(
+struct link_encoder *get_temp_dio_link_enc(
                const struct resource_context *res_ctx,
                const struct resource_pool *const pool,
                const struct dc_link *link)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 8280e3652171f44068a09af7ee3e9912ebe35063..9c9947fc5d44291139a4113fda8d56eef34351d2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1153,9 +1153,12 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
        struct timing_generator *tg = pipe_ctx->stream_res.tg;
        struct dtbclk_dto_params dto_params = {0};
        int dp_hpo_inst;
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
 
+       if (!dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+
        if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
                pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
                        pipe_ctx->stream_res.stream_enc);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index b158eb1045a19dcc3a917dd6c326e624f2a0922c..a5a3e0823e21b2cac2e4b8539712b4299710c682 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -3020,9 +3020,12 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
        enum phyd32clk_clock_source phyd32clk;
        int dp_hpo_inst;
 
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
 
+       if (!dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+
        if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
                dto_params.otg_inst = tg->inst;
                dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index c4a37a95e8124ffb66fb426b28f629ac7d9464d3..39668d8cc13a4050e384efce6ff29592d1ce280f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -927,9 +927,12 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)
        int dp_hpo_inst = 0;
        unsigned int tmds_div = PIXEL_RATE_DIV_NA;
        unsigned int unused_div = PIXEL_RATE_DIV_NA;
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
 
+       if (!dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+
        dcn401_enable_stream_calc(pipe_ctx, &dp_hpo_inst, &phyd32clk,
                                &tmds_div, &early_control);
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 042e04f924a2fe24b67de7f660b3d4b5633c9503..9458187b834d911b95262fd5863a2e773990dba7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -647,4 +647,9 @@ void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuratio
 int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master);
 
 bool resource_is_hpo_acquired(struct dc_state *context);
+
+struct link_encoder *get_temp_dio_link_enc(
+               const struct resource_context *res_ctx,
+               const struct resource_pool *const pool,
+               const struct dc_link *link);
 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */

diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
index 06faa461067b7d0f3cd3b11e6473876f4fc6ab93..4a3578a9586ed98c1e923c0724dbde6fa9916c69 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
@@ -48,9 +48,16 @@ void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,
 
 void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
 
+       if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       if (!link_enc) {
+               ASSERT(link_enc);
+               return;
+       }
+
        link_enc->funcs->connect_dig_be_to_fe(link_enc,
                        pipe_ctx->stream_res.stream_enc->id, true);
        if (dc_is_dp_signal(pipe_ctx->stream->signal))
@@ -71,9 +78,16 @@ void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
 
 void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
 
+       if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       if (!link_enc) {
+               ASSERT(link_enc);
+               return;
+       }
+
        if (!stream_enc)
                return;
 
@@ -142,7 +156,14 @@ void enable_dio_dp_link_output(struct dc_link *link,
                enum clock_source_id clock_source,
                const struct dc_link_settings *link_settings)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link_enc) {
+               ASSERT(link_enc);
+               return;
+       }
 
        if (dc_is_dp_sst_signal(signal))
                link_enc->funcs->enable_dp_output(
@@ -162,11 +183,16 @@ void disable_dio_link_output(struct dc_link *link,
                const struct link_resource *link_res,
                enum signal_type signal)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
 
-       if (link_enc != NULL)
-               link_enc->funcs->disable_output(link_enc, signal);
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link_enc) {
+               ASSERT(link_enc);
+               return;
+       }
 
+       link_enc->funcs->disable_output(link_enc, signal);
        link->dc->link_srv->dp_trace_source_sequence(link,
                        DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
 }
@@ -175,7 +201,14 @@ void set_dio_dp_link_test_pattern(struct dc_link *link,
                const struct link_resource *link_res,
                struct encoder_set_dp_phy_pattern_param *tp_params)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link_enc) {
+               ASSERT(link_enc);
+               return;
+       }
 
        link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params);
        link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
@@ -186,7 +219,14 @@ void set_dio_dp_lane_settings(struct dc_link *link,
                const struct dc_link_settings *link_settings,
                const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link_enc) {
+               ASSERT(link_enc);
+               return;
+       }
 
        link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings);
 }
@@ -195,9 +235,15 @@ void update_dio_stream_allocation_table(struct dc_link *link,
                const struct link_resource *link_res,
                const struct link_mst_stream_allocation_table *table)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link_enc) {
+               ASSERT(link_enc);
+               return;
+       }
 
-       ASSERT(link_enc);
        link_enc->funcs->update_mst_stream_allocation_table(link_enc, table);
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
index a6d1d7641ab4db098d666ea5d20e436d1a6ad033..e1dff4e3f4463752206da3447cd424fd2f85cc6d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
@@ -127,7 +127,10 @@ static void set_dio_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *lin
                const struct link_resource *link_res,
                struct encoder_set_dp_phy_pattern_param *tp_params)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
 
        if (!set_dio_fixed_vs_pe_retimer_dp_link_test_pattern_override(
                        link, link_res, tp_params, get_dio_link_hwss())) {

diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
index 36adf95744fecd2596265e5cde20bb009561f294..81d5085e322f21bb215ae8a25972ed1b2df69213 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
@@ -35,12 +35,15 @@ static void update_dpia_stream_allocation_table(struct dc_link *link,
                const struct link_resource *link_res,
                const struct link_mst_stream_allocation_table *table)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
        static enum dc_status status;
        uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
        int i;
        DC_LOGGER_INIT(link->ctx->logger);
 
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+
        for (i = 0; i < table->stream_count; i++)
                mst_alloc_slots += table->stream_allocations[i].slot_count;
 
@@ -61,7 +64,10 @@ static void set_dio_dpia_link_test_pattern(struct dc_link *link,
        if (tp_params->dp_phy_pattern != DP_TEST_PATTERN_VIDEO_MODE)
                return;
 
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
 
        if (!link_enc)
                return;
@@ -83,7 +89,10 @@ static void enable_dpia_link_output(struct dc_link *link,
                enum clock_source_id clock_source,
                const struct dc_link_settings *link_settings)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
 
        if (link_enc != NULL) {
                if (link->dc->config.enable_dpia_pre_training && link_enc->funcs->enable_dpia_output) {
@@ -119,7 +128,10 @@ static void disable_dpia_link_output(struct dc_link *link,
                const struct link_resource *link_res,
                enum signal_type signal)
 {
-       struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+       struct link_encoder *link_enc = link_res->dio_link_enc;
+
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
 
        if (link_enc != NULL) {
                if (link->dc->config.enable_dpia_pre_training && link_enc->funcs->disable_dpia_output) {

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index ec7de9c01fab0196928cbdc48521beb3b18fae4b..321fd1785370197cd2d3941e7818176611723baf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -652,15 +652,15 @@ static void write_i2c_redriver_setting(
 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
 {
        struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
-       struct link_encoder *link_enc = NULL;
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct cp_psp_stream_config config = {0};
        enum dp_panel_mode panel_mode =
                        dp_get_panel_mode(pipe_ctx->stream->link);
 
        if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
                return;
-
-       link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+       if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
        ASSERT(link_enc);
        if (link_enc == NULL)
                return;
@@ -1924,7 +1924,7 @@ static void disable_link_dp(struct dc_link *link,
 
        if (link_dp_get_encoding_format(&link_settings) ==
                        DP_8b_10b_ENCODING) {
-               dp_set_fec_enable(link, false);
+               dp_set_fec_enable(link, link_res, false);
                dp_set_fec_ready(link, link_res, false);
        }
 }
@@ -2122,7 +2122,7 @@ static enum dc_status enable_link_dp(struct dc_state *state,
                fec_enable = true;
 
        if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
-               dp_set_fec_enable(link, fec_enable);
+               dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable);
 
        // during mode set we do DP_SET_POWER off then on, aux writes are lost
        if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
@@ -2461,7 +2461,7 @@ void link_set_dpms_on(
        struct dc_stream_state *stream = pipe_ctx->stream;
        struct dc_link *link = stream->sink->link;
        enum dc_status status;
-       struct link_encoder *link_enc;
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
        struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
        const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
@@ -2486,7 +2486,8 @@ void link_set_dpms_on(
                }
        }
 
-       link_enc = link_enc_cfg_get_link_enc(link);
+       if (!dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
        ASSERT(link_enc);
 
        if (!dc_is_virtual_signal(pipe_ctx->stream->signal)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index e3e7fcb07f196924a081df1619186837fdf306ce..f6e0868507f7d443492f0b527def4c11f1fbadbe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -330,9 +330,12 @@ bool dp_is_fec_supported(const struct dc_link *link)
        /* TODO - use asic cap instead of link_enc->features
         * we no longer know which link enc to use for this link before commit
         */
-       struct link_encoder *link_enc = NULL;
+       struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
+       struct resource_pool *res_pool = link->dc->res_pool;
+       struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
 
-       link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
        ASSERT(link_enc);
 
        return (dc_is_dp_signal(link->connector_signal) && link_enc &&
@@ -2093,14 +2096,17 @@ void detect_edp_sink_caps(struct dc_link *link)
 
 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
 {
-       struct link_encoder *link_enc = NULL;
+       struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
+       struct resource_pool *res_pool = link->dc->res_pool;
+       struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
 
        if (!max_link_enc_cap) {
                DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
                return false;
        }
 
-       link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
        ASSERT(link_enc);
 
        if (link_enc && link_enc->funcs->get_max_link_cap) {
@@ -2128,10 +2134,13 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
        struct dc_link_settings max_link_cap = {0};
        enum dc_link_rate lttpr_max_link_rate;
        enum dc_link_rate cable_max_link_rate;
-       struct link_encoder *link_enc = NULL;
+       struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
+       struct resource_pool *res_pool = link->dc->res_pool;
+       struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
        bool is_uhbr13_5_supported = true;
 
-       link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
        ASSERT(link_enc);
 
        /* get max link encoder capability */

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h
index 8f0ce97f23621735759570bbfab3ccfab7f71d99..0ce0af3ddbebe72b8633899a1607ddfad37f6757 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h
@@ -67,6 +67,7 @@ bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx);
 /* Initialize output parameter lt_settings. */
 void dp_decide_training_settings(
        struct dc_link *link,
+       const struct link_resource *link_res,
        const struct dc_link_settings *link_setting,
        struct link_training_settings *lt_settings);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
index c27ffec5d84fb2ddc54bafa1a34acb265054a197..49521ac4b0e85338bb7fc93c079eba45216ec700 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
@@ -142,11 +142,12 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource
         * if the sink supports it and leave it enabled on link.
         * If FEC is not supported, disable it.
         */
-       struct link_encoder *link_enc = NULL;
+       struct link_encoder *link_enc = link_res->dio_link_enc;
        enum dc_status status = DC_OK;
        uint8_t fec_config = 0;
 
-       link_enc = link_enc_cfg_get_link_enc(link);
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
        ASSERT(link_enc);
        if (link_enc->funcs->fec_set_ready == NULL)
                return DC_NOT_SUPPORTED;
@@ -176,13 +177,14 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource
        return status;
 }
 
-void dp_set_fec_enable(struct dc_link *link, bool enable)
+void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable)
 {
-       struct link_encoder *link_enc = NULL;
+       struct link_encoder *link_enc = link_res->dio_link_enc;
 
-       link_enc = link_enc_cfg_get_link_enc(link);
-       ASSERT(link_enc);
-       if (link_enc->funcs->fec_set_enable == NULL)
+       if (!link->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
+
+       if (link_enc == NULL || link_enc->funcs == NULL || link_enc->funcs->fec_set_enable == NULL)
                return;
 
        if (enable && dp_should_enable_fec(link)) {

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h
index 1eb0619d6710e4ac7f1ae5bdad228e94134e6812..ab1c1f8f1f8b8eefab9366c64ec16a474cbb201d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h
@@ -52,7 +52,8 @@ void dp_set_drive_settings(
 enum dc_status dp_set_fec_ready(struct dc_link *link,
                const struct link_resource *link_res, bool ready);
 
-void dp_set_fec_enable(struct dc_link *link, bool enable);
+void dp_set_fec_enable(struct dc_link *link,
+               const struct link_resource *link_res, bool enable);
 
 void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index 751c18e592ea5ef1cd774de0dbf687a38f011ec1..40ac17ba94796dabb0e058e0e329ec0ae3b7b92f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -801,19 +801,23 @@ enum dc_dp_training_pattern decide_cr_training_pattern(
 }
 
 enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
+               const struct link_resource *link_res,
                const struct dc_link_settings *link_settings)
 {
-       struct link_encoder *link_enc;
+       struct link_encoder *link_enc = link_res->dio_link_enc;
        struct encoder_feature_support *enc_caps;
        struct dpcd_caps *rx_caps = &link->dpcd_caps;
        enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
 
-       link_enc = link_enc_cfg_get_link_enc(link);
-       ASSERT(link_enc);
-       enc_caps = &link_enc->features;
-
        switch (link_dp_get_encoding_format(link_settings)) {
        case DP_8b_10b_ENCODING:
+               if (!link->dc->config.unify_link_enc_assignment)
+                       link_enc = link_enc_cfg_get_link_enc(link);
+
+               if (!link_enc)
+                       break;
+
+               enc_caps = &link_enc->features;
                if (enc_caps->flags.bits.IS_TPS4_CAPABLE &&
                                rx_caps->max_down_spread.bits.TPS4_SUPPORTED)
                        pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
@@ -886,13 +890,14 @@ void dp_decide_lane_settings(
 
 void dp_decide_training_settings(
                struct dc_link *link,
+               const struct link_resource *link_res,
                const struct dc_link_settings *link_settings,
                struct link_training_settings *lt_settings)
 {
        if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
-               decide_8b_10b_training_settings(link, link_settings, lt_settings);
+               decide_8b_10b_training_settings(link, link_res, link_settings, lt_settings);
        else if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING)
-               decide_128b_132b_training_settings(link, link_settings, lt_settings);
+               decide_128b_132b_training_settings(link, link_res, link_settings, lt_settings);
 }
 
 
@@ -1556,6 +1561,7 @@ enum link_training_result dp_perform_link_training(
        /* decide training settings */
        dp_decide_training_settings(
                        link,
+                       link_res,
                        link_settings,
                        &lt_settings);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h
index 0b18aa35c33cb762846583616bfc74d9c9a4d15a..574b083e093690bc9f3f7554e9be6336b5ff22b8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h
@@ -104,6 +104,7 @@ void start_clock_recovery_pattern_early(struct dc_link *link,
 
 void dp_decide_training_settings(
                struct dc_link *link,
+               const struct link_resource *link_res,
                const struct dc_link_settings *link_settings,
                struct link_training_settings *lt_settings);
 
@@ -117,6 +118,7 @@ enum dc_dp_training_pattern decide_cr_training_pattern(
                const struct dc_link_settings *link_settings);
 
 enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
+               const struct link_resource *link_res,
                const struct dc_link_settings *link_settings);
 
 enum lttpr_mode dp_decide_lttpr_mode(struct dc_link *link,

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
index db87cfe37b5c952db91a1d49738fc27fd3171c63..11565f187ac77e9c2a0897e71d5b8fe734806b48 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
@@ -204,6 +204,7 @@ enum link_training_result dp_perform_128b_132b_link_training(
                struct link_training_settings legacy_settings;
 
                decide_8b_10b_training_settings(link,
+                               link_res,
                                &lt_settings->link_settings,
                                &legacy_settings);
                return dp_perform_8b_10b_link_training(link, link_res, &legacy_settings);
@@ -227,6 +228,7 @@ enum link_training_result dp_perform_128b_132b_link_training(
 }
 
 void decide_128b_132b_training_settings(struct dc_link *link,
+               const struct link_resource *link_res,
                const struct dc_link_settings *link_settings,
                struct link_training_settings *lt_settings)
 {
@@ -238,7 +240,7 @@ void decide_128b_132b_training_settings(struct dc_link *link,
                        LINK_SPREAD_05_DOWNSPREAD_30KHZ;
 
        lt_settings->pattern_for_cr = decide_cr_training_pattern(link_settings);
-       lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_settings);
+       lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_settings);
        lt_settings->eq_pattern_time = 2500;
        lt_settings->eq_wait_time_limit = 400000;
        lt_settings->eq_loop_count_limit = 20;

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h
index 2147f24efc8bf3e5e54af350ac1c5456ad9bd6be..901a42edafa100fc616ce3778741ac5fd065cd35 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h
@@ -34,6 +34,7 @@ enum link_training_result dp_perform_128b_132b_link_training(
                struct link_training_settings *lt_settings);
 
 void decide_128b_132b_training_settings(struct dc_link *link,
+               const struct link_resource *link_res,
                const struct dc_link_settings *link_settings,
                struct link_training_settings *lt_settings);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
index ae95ec48e572194b7801c104749f8defce124e40..34d2e097ca2e6b24217d8aff25cd45646bc154ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
@@ -93,7 +93,8 @@ static uint32_t get_eq_training_aux_rd_interval(
 }
 
 void decide_8b_10b_training_settings(
-        struct dc_link *link,
+       struct dc_link *link,
+       const struct link_resource *link_res,
        const struct dc_link_settings *link_setting,
        struct link_training_settings *lt_settings)
 {
@@ -115,7 +116,7 @@ void decide_8b_10b_training_settings(
                        LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;
        lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
        lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
-       lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
+       lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting);
        lt_settings->enhanced_framing = 1;
        lt_settings->should_set_fec_ready = true;
        lt_settings->disallow_per_lane_settings = true;

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h
index d26de15ce954e19a90a122723267113bcc31bc23..ea0de701d83f63b0021800ec15fa10d5ecf0333e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h
@@ -54,7 +54,8 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(
 enum lttpr_mode dp_decide_8b_10b_lttpr_mode(struct dc_link *link);
 
 void decide_8b_10b_training_settings(
-        struct dc_link *link,
+       struct dc_link *link,
+       const struct link_resource *link_res,
        const struct dc_link_settings *link_setting,
        struct link_training_settings *lt_settings);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c
index 4c6b886a9da8cf490dcf777c8bba0b85c87df331..f99d26290bc0ad31f3e9de6602356ae6a67a9ea6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c
@@ -39,6 +39,7 @@ bool dp_perform_link_training_skip_aux(
 
        dp_decide_training_settings(
                        link,
+                       link_res,
                        link_setting,
                        &lt_settings);
        override_training_settings(

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
index 39e4b7dc9588f4935413c42520e3acde45cafd32..6e2d08cfc5463bc0ca8a5c6f1389f4f8ac6b139d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
@@ -110,6 +110,7 @@ static enum link_training_result dpia_configure_link(
 
        dp_decide_training_settings(
                link,
+               link_res,
                link_setting,
                lt_settings);
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index 5c6dc710e96ccc9f274f083abcee7d39cc8c21b7..e4eca3e32c1b26fde539a54f5fe9319e302ee593 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -1220,7 +1220,7 @@ static void get_pixel_clock_parameters(
        struct pipe_ctx *odm_pipe;
        int opp_cnt = 1;
        struct dc_link *link = stream->link;
-       struct link_encoder *link_enc = NULL;
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct dc *dc = pipe_ctx->stream->ctx->dc;
        struct dce_hwseq *hws = dc->hwseq;
 
@@ -1229,7 +1229,8 @@ static void get_pixel_clock_parameters(
 
        pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
 
-       link_enc = link_enc_cfg_get_link_enc(link);
+       if (!dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
        if (link_enc)
                pixel_clk_params->encoder_object_id = link_enc->id;
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 4e842f29d4c49b9df7d4a9688a7c310831ee0485..7436dfbdf927af9a44832f90e18a3030bd743fcf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1666,12 +1666,13 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
 {
        const struct dc_stream_state *stream = pipe_ctx->stream;
        struct dc_link *link = stream->link;
-       struct link_encoder *link_enc = NULL;
+       struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
        struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
 
        pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
 
-       link_enc = link_enc_cfg_get_link_enc(link);
+       if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
+               link_enc = link_enc_cfg_get_link_enc(link);
        if (link_enc)
                pixel_clk_params->encoder_object_id = link_enc->id;