Run gdb/contrib/spellcheck.sh on directory sim.
Fix auto-corrected typos:
...
accessable -> accessible
accidently -> accidentally
accomodate -> accommodate
adress -> address
afair -> affair
agains -> against
agressively -> aggressively
annuled -> annulled
arbitary -> arbitrary
arround -> around
auxillary -> auxiliary
availablity -> availability
clasic -> classic
comming -> coming
controled -> controlled
controling -> controlling
destory -> destroy
existance -> existence
explictly -> explicitly
faciliate -> facilitate
fouth -> fourth
fullfilled -> fulfilled
guarentee -> guarantee
hinderance -> hindrance
independant -> independent
inital -> initial
loosing -> losing
occurance -> occurrence
occured -> occurred
occuring -> occurring
omited -> omitted
oportunity -> opportunity
parallely -> parallelly
permissable -> permissible
postive -> positive
powerfull -> powerful
preceed -> precede
preceeding -> preceding
preceeds -> precedes
primative -> primitive
probaly -> probably
programable -> programmable
propogate -> propagate
propper -> proper
recieve -> receive
reconized -> recognized
refered -> referred
refering -> referring
relevent -> relevant
responisble -> responsible
retreive -> retrieve
safty -> safety
specifiying -> specifying
spontanous -> spontaneous
sqaure -> square
successfull -> successful
supress -> suppress
sytem -> system
thru -> through
transfered -> transferred
trigered -> triggered
unfortunatly -> unfortunately
upto -> up to
usefull -> useful
wierd -> weird
writen -> written
doesnt -> doesn't
isnt -> isn't
...
Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs
and sim/cr16/simops.c.
Tested by rebuilding on x86_64-linux.
Approved-By: Tom Tromey <tom@tromey.com>
an out-of-memory condition by noticing a stack/heap collision.
The heap starts at the end of loaded memory and carries on up
- to an arbitary 2Gb limit. */
+ to an arbitrary 2Gb limit. */
uint64_t
aarch64_get_heap_start (sim_cpu *cpu)
return ARMul_CANT;
break;
case 7:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
break;
case 8:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
/* Writes are not allowed. */
return;
- case 1: /* Auxillary Control. */
+ case 1: /* Auxiliary Control. */
/* Only BITS (5, 4) and BITS (1, 0) can be written. */
value &= 0x33;
break;
hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking
- care to propogate the carries from the additions. */
+ care to propagate the carries from the additions. */
RdLo = Add32 (lo, (mid1 << 16), &carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), &carry);
#include "bfin-sim.h"
-/* We keep the same inital structure layout with DMA enabled devices. */
+/* We keep the same initial structure layout with DMA enabled devices. */
struct dv_bfin {
bu32 base;
struct hw *dma_master;
/* XXX: what happens with 'raise 0' ? */
SET_RETEREG (oldpc);
excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
- /* XXX: Need an easy way for gdb to signal it isnt here. */
+ /* XXX: Need an easy way for gdb to signal it isn't here. */
cec->ipend &= ~IVG_EMU_B;
break;
case IVG_RST:
non-zero 32 bit big-endian value to this register sets the
countdown timer to expire in VALUE ticks (ticks is target
dependant). Reading the countdown register returns the last value
- writen.
+ written.
COUNTDOWN VALUE (read): Reading this 32 bit big-endian register
returns the number of ticks remaining until the countdown timer
#ifndef HW_BASE
#define HW_BASE
-/* Create a primative device */
+/* Create a primitive device */
struct hw *hw_create
(struct sim_state *sd,
/* Hardware operations:
Connecting a parent to its children is a common bus. The parent
- node is described as the bus owner and is responisble for
+ node is described as the bus owner and is responsible for
co-ordinating bus operations. On the bus, a SPACE:ADDR pair is used
to specify an address. A device that is both a bus owner (parent)
and bus client (child) are referred to as a bridging device.
disks file system. The operations would be implemented using the
basic block I/O model provided by the disk.
- This model includes methods that faciliate the creation of device
+ This model includes methods that facilitate the creation of device
instance and (should a given device support it) standard operations
on those instances.
/* parse the path */
split_device_specifier (root, path_to_device, &spec);
if (spec.value != NULL)
- return NULL; /* something wierd */
+ return NULL; /* something weird */
/* now find it */
node = split_find_device (root, &spec);
{
if (! delete_p)
{
- /* Try next range if current range preceeds new one and not
+ /* Try next range if current range precedes new one and not
adjacent or overlapping. */
if (asr->end < caller->start - 1)
goto next_range;
- /* Break out if new range preceeds current one and not
+ /* Break out if new range precedes current one and not
adjacent or overlapping. */
if (asr->start > caller->end + 1)
break;
}
else /* deleting a range */
{
- /* Try next range if current range preceeds new one. */
+ /* Try next range if current range precedes new one. */
if (asr->end < caller->start)
goto next_range;
- /* Break out if new range preceeds current one. */
+ /* Break out if new range precedes current one. */
if (asr->start > caller->end)
break;
/* some rotate functions. The generic macro's ROT, ROTL, ROTR are
- intentionally omited. */
+ intentionally omitted. */
INLINE_SIM_BITS(uint8_t) ROT8 (uint8_t val, int shift);
expect to see (VEA includes things like coherency and the time
base) while OEA is what an operating system expects to see. By
setting these to specific values, the build process is able to
- eliminate non relevent environment code.
+ eliminate non relevant environment code.
STATE_ENVIRONMENT(sd) specifies which of vea or oea is required for
the current runtime.
such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
(OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal
hook that allows clients to do nasty things that the interface doesn't
- accomodate. */
+ accommodate. */
extern void sim_core_attach
(SIM_DESC sd,
Transfer a variable sized block of raw data between the host and
target. Should any problems occur, the number of bytes
- successfully transfered is returned.
+ successfully transferred is returned.
No host/target byte endian conversion is performed. No xor-endian
conversion is performed.
Transfer a variable sized block of raw data between the host and
target. Should any problems occur, the number of bytes
- successfully transfered is returned.
+ successfully transferred is returned.
No host/target byte endian conversion is performed. If applicable
(WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
/* Fixed sized, processor oriented, read/write.
Transfer a fixed amout of memory between the host and target. The
- data transfered is translated from/to host to/from target byte
+ data transferred is translated from/to host to/from target byte
order (including xor endian). Should the transfer fail, the
operation shall abort (no return).
/* Called by the generic sim_resume to run the simulation within the
- above safty net.
+ above safety net.
An example implementation of sim_engine_run can be found in the
file sim-run.c */
speed improvement (x3-x5). In the case of RISC (sparc) while the
performance gain isn't as great it is still significant.
- Each module is controled by the macro <module>_INLINE which can
+ Each module is controlled by the macro <module>_INLINE which can
have the values described below
0 (ZERO)
FIXME: Some completly new mechanism for handling the general
problem of asynchronous IO is needed.
- FIXME: This function does not supress the echoing (ECHO) of input.
+ FIXME: This function does not suppress the echoing (ECHO) of input.
Consequently polled input is always displayed.
FIXME: This function does not perform uncooked reads.
}
-/* Generic resume - assumes the existance of sim_engine_run */
+/* Generic resume - assumes the existence of sim_engine_run */
void
sim_resume (SIM_DESC sd,
hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
reg_lo = add32 (lo, (mid1 << 16), &carry);
reg_hi = carry;
reg_lo = add32 (reg_lo, (mid2 << 16), &carry);
FPU. IEEE trap handling is done as follows:
1. In the host, all IEEE traps are masked
2. After each simulated FPU instruction, check if any exception
- occured by reading the exception bits from the host FPU status
+ occurred by reading the exception bits from the host FPU status
register (get_accex()).
3. Propagate any exceptions to the simulated FSR.
4. Clear host exception bits.
uint64_t pwdtime; /* Cycles in power-down mode */
uint64_t nstore; /* Number of load instructions */
uint64_t nload; /* Number of store instructions */
- uint64_t nannul; /* Number of annuled instructions */
+ uint64_t nannul; /* Number of annulled instructions */
uint64_t nbranch; /* Number of branch instructions */
uint32_t ildreg; /* Destination of last load instruction */
uint64_t ildtime; /* Last time point for load dependency */
/* FR-V Interrupt.
This struct contains enough information to describe a particular interrupt
- occurance. */
+ occurrence. */
struct frv_interrupt
{
enum frv_interrupt_kind kind;
}
/* Run the insn and data caches through the given number of cycles, taking
- note of load requests which are fullfilled as a result. */
+ note of load requests which are fulfilled as a result. */
static void
run_caches (SIM_CPU *cpu, int cycles)
{
FRV_CACHE* data_cache = CPU_DATA_CACHE (cpu);
FRV_CACHE* insn_cache = CPU_INSN_CACHE (cpu);
int i;
- /* For each cycle, run the caches, noting which requests have been fullfilled
+ /* For each cycle, run the caches, noting which requests have been fulfilled
and submitting new requests on their designated cycles. */
for (i = 0; i < cycles; ++i)
{
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
return;
- /* Adress must be aligned on a word boundary. */
+ /* Address must be aligned on a word boundary. */
if (address & 0x3)
frv_queue_data_access_exception_interrupt (current_cpu);
}
return store_1 (sd, arg, n, 1);
}
-/* Callback for qsort. We sort first based on availablity
+/* Callback for qsort. We sort first based on availability
(available instructions sort lower). When availability state
is the same, then we use the first 4 bit nibble as a secondary
sort key.
{
/* Output the function to execute real code:
- Unfortunatly, there are multiple cases to consider vis:
+ Unfortunately, there are multiple cases to consider vis:
<icache> X <smp>
switch (what_to_declare)
{
case undef_variables:
- /* We've finished with the #define value - destory it */
+ /* We've finished with the #define value - destroy it */
lf_indent_suppress (file);
lf_printf (file, "#undef %s\n", entry_name);
return;
else
{
/* alernativly, since no cache, emit a dummy definition for
- idecode_cache so that code refering to the type can still compile */
+ idecode_cache so that code referring to the type can still compile */
lf_printf (file, "typedef void %sidecode_cache;\n",
options.module.global.prefix.l);
}
}
/* Architecture expects a REG to be zero. Instead of having to
- check every read to see if it is refering to that REG just zap it
+ check every read to see if it is referring to that REG just zap it
at the start of every instruction */
if (options.gen.zero_reg)
{
o cached - separate cracker and semantic
- Two independant functions are created. Firstly the
+ Two independent functions are created. Firstly the
function that cracks an instruction entering it into a
- cache and secondly the semantic function propper that
+ cache and secondly the semantic function proper that
uses the cache.
o cached - semantic + cracking semantic
/* Given only one constant value has been found, check through all
the instructions to see if at least one conditional makes it
- usefull */
+ useful */
if (value >= 0 && is_useless)
{
for (entry = insns; entry != NULL; entry = entry->next)
condition->field->last);
/* this is a requirement of
a conditonal field
- refering to another field */
+ referring to another field */
ASSERT ((condition->field->first -
condition->field->last) ==
(first_pos - last_pos));
{
/* NB: Here we escape each EOLN. This is so that the the compiler
treats a trace function call as a single line. Consequently any
- errors in the line are refered back to the same igen assembler
+ errors in the line are referred back to the same igen assembler
source line */
const char *phase = (idecode) ? "DECODE" : "INSN";
lf_printf (file, "\n");
int combine;
/* Instruction expansion? Should the semantic code for each
- instruction, when the oportunity arrises, be expanded according
+ instruction, when the opportunity arrises, be expanded according
to the variable opcode files that the instruction decode process
renders constant */
int duplicate;
else
new_rule->last = options.insn_bit_size - 1;
if (new_rule->first > new_rule->last)
- error (new_rule->line, "First must preceed last\n");
+ error (new_rule->line, "First must precede last\n");
/* force first/last, with default values based on first/last */
if (entry->nr_fields > decode_force_first_field
If an instruction field was found, enlarge the field size so that
it is forced to at least include bits starting from <force_first>
- (<force_last>). To stop this occuring, use <force_first> = <last>
+ (<force_last>). To stop this occurring, use <force_first> = <last>
+ 1 and <force_last> = <first> - 1.
<force_reserved>
Treat any contained register (string) fields as constant when
determining the instruction field. For the instruction decode (and
- controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+ controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
what would otherwize be non constant bits of an instruction.
<use_switch>
{
if (strlen_pos == 0)
{
- /* when the length/pos field is omited, an integer field
+ /* when the length/pos field is omitted, an integer field
is always binary */
uint64_t val = 0;
int i;
insn->word[i] = word;
}
- /* Go over all fields that have conditionals refering to other
+ /* Go over all fields that have conditionals referring to other
fields. Link the fields up. Verify that the two fields have the
same size. Verify that the two fields are different */
{
&& strcmp (refered_field->val_string,
cond->string) == 0)
{
- /* found field being refered to by conditonal */
+ /* found field being referred to by conditonal */
cond->field = refered_field;
- /* check refered to and this field are
+ /* check referred to and this field are
the same size */
if (f->width != refered_field->width)
error (insn->line,
/* Open the file NAME for writing ("-" for stdout). Use REAL_NAME
- when refering to the opened file. Line number information (in the
+ when referring to the opened file. Line number information (in the
output) can be suppressed with FILE_REFERENCES ==
LF_OMIT_REFERENCES. TYPE is to determine the formatting of some of
the print messages below. */
hw_port_event (me, INT_PORT, 1);
}
- /* Indicate which interrupt has occured. */
+ /* Indicate which interrupt has occurred. */
uart->iir = MICOUART_IIR_TXRDY;
/* Indicate THR is empty. */
with the first insn. */
/* ??? Revisit to handle exceptions right. */
- /* FIXME: No need to handle this parallely if second is nop. */
+ /* FIXME: No need to handle this parallelly if second is nop. */
id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
/* Note that this can never be a cti. No cti's go in the S pipeline. */
with the first insn. */
/* ??? Revisit to handle exceptions right. */
- /* FIXME: No need to handle this parallely if second is nop. */
+ /* FIXME: No need to handle this parallelly if second is nop. */
id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
/* Note that this can never be a cti. No cti's go in the S pipeline. */
/* TODO: These functions are a big hack and assume that the host runtime has
type sizes and struct layouts that match the target. So the Linux emulation
- probaly only really works in 32-bit runtimes. */
+ probably only really works in 32-bit runtimes. */
static void
translate_endian_h2t (void *addr, size_t size)
compare = (m68hc11_cpu->ios[i] << 8) + m68hc11_cpu->ios[i + 1];
- /* See if compare is reached; handle wrap arround. */
+ /* See if compare is reached; handle wrap around. */
if ((compare >= tcnt_prev && compare <= tcnt && tcnt_prev < tcnt)
|| (compare >= tcnt_prev && tcnt_prev > tcnt)
|| (compare < tcnt && tcnt_prev > tcnt))
for fc in ${sim_mips_multi_configs}; do
dnl Split up the entry. ${c} contains the first three elements.
- dnl Note: outer sqaure brackets are m4 quotes.
+ dnl Note: outer square brackets are m4 quotes.
c=`echo ${fc} | sed ['s/:[^:]*$//']`
bfdmachs=`echo ${fc} | sed 's/.*://'`
name=`echo ${c} | sed 's/:.*//'`
}
else if (exception != 0 && mips_cpu->exc_suspended == 0)
{
- sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
+ sim_io_eprintf(sd, "Warning, ignoring spontaneous exception signal (%d)\n", exception);
}
mips_cpu->exc_suspended = 0;
}
{
if (STATE & simDELAYSLOT)
{
- return DSPC; /* return saved address of preceeding jmp */
+ return DSPC; /* return saved address of preceding jmp */
}
else
{
// suggest they don't.
//
// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
-// these restrictions, while others, like the VR5500, don't. To accomodate
+// these restrictions, while others, like the VR5500, don't. To accommodate
// such differences, the MIPS IV and MIPS V version of these helper functions
-// use auxillary routines to determine whether the restriction applies.
+// use auxiliary routines to determine whether the restriction applies.
// check_mf_cycles:
//
*micromips32:
*micromips64:
{
- /* FIXME: could record the fact that a stall occured if we want */
+ /* FIXME: could record the fact that a stall occurred if we want */
int64_t time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
/* For some MIPS targets, the HI/LO registers have certain timing
restrictions in that, for instance, a read of a HI register must be
- separated by at least three instructions from a preceeding read.
+ separated by at least three instructions from a preceding read.
The struct below is used to record the last access by each of A MT,
MF or other OP instruction to a HI/LO register. See mips.igen for
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
+#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occurred */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */
sim_hw_parse (sd, "/mn103cpu@0x20000000");
sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
- /* DEBUG: ACK output wired upto a glue device */
+ /* DEBUG: ACK output wired up to a glue device */
sim_hw_parse (sd, "/glue@0x20002000");
sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4");
sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000");
}
else if(exception != 0 && State.exc_suspended == 0)
{
- sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
+ sim_io_eprintf(sd, "Warning, ignoring spontaneous exception signal (%d)\n", exception);
}
State.exc_suspended = 0;
}
PORTABILITY:
(Notes taken from Michael Meissner): Heavy use of the ## operator -
-fix using the clasic X/**/Y hack; Use of the signed keyword. In
+fix using the classic X/**/Y hack; Use of the signed keyword. In
particular, signed char has no analogue in classic C (though most
implementations of classic C use signed chars); Use of long long which
restricts the target compiler to be GCC.
Igen at present can't do the following:
- o duplication is an all or nothing afair.
+ o duplication is an all or nothing affair.
It should be configurable according to
the instruction or the sub-table.
the description of a target machine (including the initial
state of all processor registers) from a file.
- Unfortunatly GDB does not yet have a standard command that
+ Unfortunately GDB does not yet have a standard command that
facilitates the use of this feature. Until such a command is
added, the patch (hack?) gdb-4.15+attach.diff.gz can be used to
extend GDB's attach command so that it can be used to initialize
If PSIM doesn't monitor a components of interest,
the source code is freely available, and hence
- there is no hinderance to changing things
+ there is no hindrance to changing things
to meet a specific analysts needs.
The output from a performance run (on a P90) for the program
psim-test/profile/bench is below. In this run psim was fairly
-agressively configured (see the file INSTALL for compile time
+aggressively configured (see the file INSTALL for compile time
configuration).
CPU #1 executed 41,994 AND instructions.
/* AltiVec endian helpers, wrong endian hosts vs targets need to be
sure to get the right bytes/halfs/words when the order matters.
Note that many AltiVec instructions do not depend on byte order and
- work on N independant bits of data. This is only for the
+ work on N independent bits of data. This is only for the
instructions that actually move data around. */
#if (HOST_BYTE_ORDER == BIG_ENDIAN)
restarting it.
For callback maps it is possible to further order them by
- specifiying specifying a callback level (eg callback + 1).
+ specifying specifying a callback level (eg callback + 1).
When the core is resolving an access it searches each of the maps
in order. First raw-memory and then callback maps (in assending
The operation of mapping between an address and its destination
device or memory array is currently implemented using a simple
linked list. The posibility of replacing this list with a more
- powerfull data structure exists.
+ powerful data structure exists.
*/
Transfer (zero) a variable size block of data between the host and
target (possibly byte swapping it). Should any problems occure,
- the number of bytes actually transfered is returned. */
+ the number of bytes actually transferred is returned. */
INLINE_CORE\
(unsigned) core_map_read_buffer
#if WITH_IDECODE_CACHE_SIZE
-/* Return the cache entry that matches the given CIA. No guarentee
+/* Return the cache entry that matches the given CIA. No guarantee
that the cache entry actually contains the instruction for that
address */
inner vm maps, to have the cpu its self provide memory manipulation
functions. (eg cpu_instruction_fetch() cpu_data_read_4())
- Unfortunatly in addition to these functions is the need (for the
+ Unfortunately in addition to these functions is the need (for the
debugger) to be able to read/write to memory in ways that violate
the vm protection (eg store breakpoint instruction in the
instruction map). */
static trace_option_descriptor trace_description[] = {
{ trace_gdb, "gdb", "calls made by gdb to the sim_calls.c file" },
- { trace_os_emul, "os-emul", "VEA mode sytem calls - like strace" },
+ { trace_os_emul, "os-emul", "VEA mode system calls - like strace" },
{ trace_events, "events", "event queue handling" },
/* decode/issue */
{ trace_semantics, "semantics", "Instruction execution (issue)" },
disks file system. The operations would be implemented using the
basic block I/O model provided by the disk.
- This model includes methods that faciliate the creation of device
+ This model includes methods that facilitate the creation of device
instance and (should a given device support it) standard operations
on those instances.
#define _NETWR 0x019 /* Write to host */
#define _NETCFIG 0x01a /* Configure network parameters */
#define _NETOPN 0x01b /* Open file for reading */
-#define _NETFRD 0x01c /* Retreive specified file blocks */
+#define _NETFRD 0x01c /* Retrieve specified file blocks */
#define _NETCTRL 0x01d /* Implement special control functions */
#define _OUTCHR 0x020 /* Output character (pointer / pointer format) */
#define _OUTSTR 0x021 /* Output string (pointer / pointer format) */
{ _NETWR, ".NETWR -- Write to host" },
{ _NETCFIG, ".NETCFIG -- Configure network parameters" },
{ _NETOPN, ".NETOPN -- Open file for reading" },
- { _NETFRD, ".NETFRD -- Retreive specified file blocks" },
+ { _NETFRD, ".NETFRD -- Retrieve specified file blocks" },
{ _NETCTRL, ".NETCTRL -- Implement special control functions" },
{ _OUTCHR, ".OUTCHR -- Output character" },
{ _OUTSTR, ".OUTSTR -- Output string (pointer / pointer format)" },
/* Define a storage area for the cache element */
if (what_to_declare == undef_variables) {
- /* We've finished with the value - destory it */
+ /* We've finished with the value - destroy it */
lf_indent_suppress(file);
lf_printf(file, "#undef %s\n", entry_name);
return;
}
else {
/* alernativly, since no cache, emit a dummy definition for
- idecode_cache so that code refering to the type can still compile */
+ idecode_cache so that code referring to the type can still compile */
lf_printf(file, "typedef void idecode_cache;\n");
}
lf_printf(file, "\n");
{
/* Output the function to execute real code:
- Unfortunatly, there are multiple cases to consider vis:
+ Unfortunately, there are multiple cases to consider vis:
<icache> X <smp> X <events> X <keep-running-flag> X ...
o cached - separate cracker and semantic
- Two independant functions are created. Firstly the
+ Two independent functions are created. Firstly the
function that cracks an instruction entering it into a
- cache and secondly the semantic function propper that
+ cache and secondly the semantic function proper that
uses the cache.
o cached - semantic + cracking semantic
/* Take the interrupt and synchronize its delivery with the clock. If
we've not yet scheduled an interrupt for the next clock tick, take
- the oportunity to do it now */
+ the opportunity to do it now */
static void
hw_cpu_interrupt_event(device *me,
/* DEVICE
- eeprom - JEDEC? compatible electricaly erasable programable device
+ eeprom - JEDEC? compatible electricaly erasable programmable device
DESCRIPTION
This device models the primary/secondary <<ide>> controller
described in the [CHRPIO] document.
- The controller has separate independant interrupt outputs for each
+ The controller has separate independent interrupt outputs for each
<<ide>> bus.
| i0,0,1c,6 1 \
| i0,0,20,0 8' \
- Note: the fouth and fifth reg entries specify that the register is
+ Note: the fourth and fifth reg entries specify that the register is
at an offset into the address specified by the base register
(<<assigned-addresses>>); Apart from restrictions placed by the
<<pci>> specification, no restrictions are placed on the number of
eeprom requires a complex sequence of accesses). The
<<real-address>> is specified as <<0x0c00>> which is the offset
into the eeprom. For brevity, most of the eeprom properties have
- been omited.
+ been omitted.
| /iobus/eeprom@0xfff00000/reg 0xfff00000 0x80000
| /openprom/init/data@0xfff00c00/real-address 0x0c00
else if (!src->is_level_triggered
&& src->is_positive_polarity
&& !asserted) {
- DTRACE(opic, ("interrupt %d - ignore falling edge (positive edge trigered)\n",
+ DTRACE(opic, ("interrupt %d - ignore falling edge (positive edge triggered)\n",
src->nr));
}
else if (!src->is_level_triggered
&& !src->is_positive_polarity
&& asserted) {
- DTRACE(opic, ("interrupt %d - ignore rising edge (negative edge trigered)\n",
+ DTRACE(opic, ("interrupt %d - ignore rising edge (negative edge triggered)\n",
src->nr));
}
else if (src->in_service != 0) {
DTRACE(opic, ("eoi %d - ignoring nonzero value\n", dest->nr));
}
- /* user doing wierd things? */
+ /* user doing weird things? */
if (dest->current_in_service == NULL) {
DTRACE(opic, ("eoi %d - strange, no current interrupt\n", dest->nr));
return;
opic_timer *timer = data;
device *me = timer->me;
if (timer->inhibited)
- device_error(timer->me, "internal-error - timer event occured when timer %d inhibited",
+ device_error(timer->me, "internal-error - timer event occurred when timer %d inhibited",
timer->nr);
handle_interrupt(timer->me, timer->opic, timer->interrupt_source, 1);
timer->timeout_event = device_event_queue_schedule(me, timer->base_count,
Since device tree entries that are specified on the command line
are added before most of the device tree has been built it is often
- necessary to explictly add certain device properties and thus
+ necessary to explicitly add certain device properties and thus
ensure they are already present in the device tree. For the
<<phb>> one such property is parent busses <<#address-cells>>.
The Open Firmware PCI bus bindings document (rev 1.6) suggests that
the register field of non-relocatable PCI address should be zero.
- Unfortunatly, PCI addresses specified in the <<assigned-addresses>>
+ Unfortunat
ely, PCI addresses specified in the <<assigned-addresses>>
property must be both non-relocatable and have non-zero register
fields.
if (phb_type != hw_phb_normal_decode && phb_type != hw_phb_subtractive_decode)
device_error(me, "attach type (%d) specified by %s invalid",
type, device_path(client));
- /* attach it to the relevent bus */
+ /* attach it to the relevant bus */
DTRACE(phb, ("attach %s - %s %s:0x%lx (0x%lx bytes)\n",
device_path(client),
hw_phb_decode_name(phb_type),
/* 64bit target expressions:
- Unfortunatly 128bit arrithemetic isn't that common. Consequently
+ Unfortunately 128bit arrithemetic isn't that common. Consequently
the 32/64 bit trick can not be used. Instead all calculations are
required to retain carry/overflow information in separate
variables. Even with this restriction it is still possible for the
printf(" -C Include semantics in cache functions\n");
printf(" -S Include insn (instruction) in icache\n");
printf(" -R Use defines to reference cache vars\n");
- printf(" -L Supress line numbering in output files\n");
+ printf(" -L Suppress line numbering in output files\n");
printf(" -B <bit-size> Set the number of bits in an instruction\n");
printf(" -H <high-bit> Set the nr of the high (msb bit)\n");
printf(" -N <nr-cpus> Specify the max number of cpus the simulation will support\n");
generate_calls = 0x100,
- /* In addition, when refering to fields access them directly instead
+ /* In addition, when referring to fields access them directly instead
of via variables */
generate_calls_with_direct_access
/* Instruction expansion?
- Should the semantic code for each instruction, when the oportunity
+ Should the semantic code for each instruction, when the opportunity
arrises, be expanded according to the variable opcode files that
the instruction decode process renders constant */
If an instruction field was found, enlarge the field size so that
it is forced to at least include bits starting from <force_first>
- (<force_last>). To stop this occuring, use <force_first> = <last>
+ (<force_last>). To stop this occurring, use <force_first> = <last>
+ 1 and <force_last> = <first> - 1.
<force_slash>
Treat any contained register (string) fields as constant when
determining the instruction field. For the instruction decode (and
- controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+ controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
what would otherwize be non constant bits of an instruction.
<use_switch>
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- double product; /*HACK! - incorrectly loosing precision ... */
+ double product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- float product; /*HACK! - incorrectly loosing precision ... */
+ float product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- double product; /*HACK! - incorrectly loosing precision ... */
+ double product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- float product; /*HACK! - incorrectly loosing precision ... */
+ float product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- double product; /*HACK! - incorrectly loosing precision ... */
+ double product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- float product; /*HACK! - incorrectly loosing precision ... */
+ float product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- double product; /*HACK! - incorrectly loosing precision ... */
+ double product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
*603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
FPSCR_BEGIN;
- float product; /*HACK! - incorrectly loosing precision ... */
+ float product; /*HACK! - incorrectly losing precision ... */
/* compute the multiply */
if (is_invalid_operation(processor, cia,
*frA, *frC,
os_emulation = os_emul_create(file_name, root);
if (os_emulation == NULL)
- error("psim: either file %s was not reconized or unreconized or unknown os-emulation type\n", file_name);
+ error("psim: either file %s was not recognized or unreconized or unknown os-emulation type\n", file_name);
/* fill in the missing real number of CPU's */
nr_cpus = tree_find_integer_property(root, "/openprom/options/smp");
processor = system->processors[which_cpu];
- /* If the data is comming in raw (target order), need to cook it
+ /* If the data is coming in raw (target order), need to cook it
into host order before putting it into PSIM's internal structures */
if (mode == raw_transfer) {
switch (description.size) {
@end ifinfo
@c Here is a spare copy of the chapter menu entry descriptions,
-@c in case they are accidently deleted
+@c in case they are accidentally deleted
@ignore
Your rights.
Texinfo in brief.
If PSIM doesn't monitor a components of interest,
the source code is freely available, and hence
- there is no hinderance to changing things
+ there is no hindrance to changing things
to meet a specific analysts needs.
expect to see (VEA includes things like coherency and the time
base) while OEA is what an operating system expects to see. By
setting these to specific values, the build process is able to
- eliminate non relevent environment code
+ eliminate non relevant environment code
CURRENT_ENVIRONMENT specifies which of vea or oea is required for
the current runtime. */
/* Events. Devices modeling real H/W need to be able to efficiently
schedule things to do at known times in the future. The event
- queue implements this. Unfortunatly this adds the need to check
+ queue implements this. Unfortunately this adds the need to check
for any events once each full instruction cycle. */
#define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT)
speed improvement (x3-x5). In the case of RISC (sparc) while the
performance gain isn't as great it is still significant.
- Each module is controled by the macro <module>_INLINE which can
+ Each module is controlled by the macro <module>_INLINE which can
have the values described below
0 Do not inline any thing for the given module
Prefix to any declaration of a global object (function or
variable) that should not be inlined and should have only one
definition. The #ifndef wrapper goes around the definition
- propper to ensure that only one copy is generated.
+ proper to ensure that only one copy is generated.
nb: this will not work when a module is being inlined for every
use.
/* parse the path */
split_device_specifier(root, path_to_device, &spec);
if (spec.value != NULL)
- return NULL; /* something wierd */
+ return NULL; /* something weird */
/* now find it */
node = split_find_device(root, &spec);
}
-/* Bring things into existance */
+/* Bring things into existence */
INLINE_VM\
(vm *)
/* generic block transfers. Dependant on the presence of the
- PROCESSOR arg, either returns the number of bytes transfered or (if
+ PROCESSOR arg, either returns the number of bytes transferred or (if
PROCESSOR is non NULL) aborts the simulation */
INLINE_VM\
/* Alternate bank of registers r0-r7 */
-/* Note: code controling SR handles flips between BANK0 and BANK1 */
+/* Note: code controlling SR handles flips between BANK0 and BANK1 */
#define Rn_BANK(n) (saved_state.asregs.bank[(n)])
#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0)
#define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
#define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
-#define SCI_RDRF 0x40 /* Recieve data register full */
+#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_TDRE 0x80 /* Transmit data register empty */
static int
mach |= 0xffff8000; /* Sign extend higher 16 bits */
}
else
- mach = mach & 0x00007fff; /* Postive Result */
+ mach = mach & 0x00007fff; /* Positive Result */
}
MACL = macl;
// Description: Multi-issue Illegal Combinations
# mach: bfin
# sim: --environment operating
-# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
+# xfail: "missing a few checks; hardware doesn't seem to match PRM?" *-*
#include "test.h"
.include "testutils.inc"
.dw 0x21 ;
.dw 0x22 ;
.dw 0x26 ;
- .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ?
+ .dw 0x27 ; // XXX: hardware doesn't trigger illegal exception ?
.dw 0x28 ;
.dw 0x29 ;
.dw 0x2A ;
.dw 0x10E ;
.dw 0x124 ;
.ifndef BFIN_HW
- // XXX: hardware doesnt trigger illegal exception ?
+ // XXX: hardware doesn't trigger illegal exception ?
.dw 0x125 ;
.endif
.dw 0x164 ;
.ifndef BFIN_HW
- // XXX: hardware doesnt trigger illegal exception ?
+ // XXX: hardware doesn't trigger illegal exception ?
.dw 0x165 ;
.endif
.dw 0x128 ;
.data
1: ldi r1, 2f@word
jmp r1
-;;; Successfull trap jumps back to here
+;;; Successful trap jumps back to here
.text
;;; Verify the PSW
2: mvfc r2, cr0
test_fr_iimmed \val,fr31
.endm
-; Test CPR agains an immediate value
+; Test CPR against an immediate value
.macro test_cpr_limmed valh vall reg
addi sp,-4,gr31
stc \reg,@(gr31,gr0)
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
- stc sbr, er1 ; retreive and check sbr value
+ stc sbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
- stc vbr, er1 ; retreive and check sbr value
+ stc vbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
- stc sbr, er1 ; retreive and check sbr value
+ stc sbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
- stc vbr, er1 ; retreive and check sbr value
+ stc vbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
mov.b @tccr\@, r0l
.endm
-; Test that all (accessable) condition codes are clear
+; Test that all (accessible) condition codes are clear
.macro test_cc_clear
test_carry_clear
test_ovf_clear
hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
RdLo = Add32 (lo, (mid1 << 16), & carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), & carry);
reg_t mpu0_sregs[28]; /* mpu0 system registers */
reg_t mpu1_sregs[28]; /* mpu1 system registers */
reg_t fpu_sregs[28]; /* fpu system registers */
- reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
+ reg_t selID_sregs[7][32]; /* system registers, selID 1 through selID 7 */
reg64_t vregs[32]; /* vector registers. */
} v850_regs;
hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
RdLo = Add32 (lo, (mid1 << 16), & carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), & carry);
hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
RdLo = Add32 (lo, (mid1 << 16), & carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), & carry);
projects / thirdparty / binutils-gdb.git / commitdiff
