--- /dev/null
+From 2b83809a5e6d619a780876fcaf68cdc42b50d28c Mon Sep 17 00:00:00 2001
+From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Date: Mon, 31 Jul 2017 10:51:59 +0200
+Subject: x86/cpu/amd: Derive L3 shared_cpu_map from cpu_llc_shared_mask
+
+From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+
+commit 2b83809a5e6d619a780876fcaf68cdc42b50d28c upstream.
+
+For systems with X86_FEATURE_TOPOEXT, current logic uses the APIC ID
+to calculate shared_cpu_map. However, APIC IDs are not guaranteed to
+be contiguous for cores across different L3s (e.g. family17h system
+w/ downcore configuration). This breaks the logic, and results in an
+incorrect L3 shared_cpu_map.
+
+Instead, always use the previously calculated cpu_llc_shared_mask of
+each CPU to derive the L3 shared_cpu_map.
+
+Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Link: http://lkml.kernel.org/r/20170731085159.9455-3-bp@alien8.de
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/cpu/intel_cacheinfo.c | 32 ++++++++++++++++++--------------
+ 1 file changed, 18 insertions(+), 14 deletions(-)
+
+--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
++++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
+@@ -811,7 +811,24 @@ static int __cache_amd_cpumap_setup(unsi
+ struct cacheinfo *this_leaf;
+ int i, sibling;
+
+- if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
++ /*
++ * For L3, always use the pre-calculated cpu_llc_shared_mask
++ * to derive shared_cpu_map.
++ */
++ if (index == 3) {
++ for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
++ this_cpu_ci = get_cpu_cacheinfo(i);
++ if (!this_cpu_ci->info_list)
++ continue;
++ this_leaf = this_cpu_ci->info_list + index;
++ for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
++ if (!cpu_online(sibling))
++ continue;
++ cpumask_set_cpu(sibling,
++ &this_leaf->shared_cpu_map);
++ }
++ }
++ } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
+ unsigned int apicid, nshared, first, last;
+
+ this_leaf = this_cpu_ci->info_list + index;
+@@ -837,19 +854,6 @@ static int __cache_amd_cpumap_setup(unsi
+ continue;
+ cpumask_set_cpu(sibling,
+ &this_leaf->shared_cpu_map);
+- }
+- }
+- } else if (index == 3) {
+- for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
+- this_cpu_ci = get_cpu_cacheinfo(i);
+- if (!this_cpu_ci->info_list)
+- continue;
+- this_leaf = this_cpu_ci->info_list + index;
+- for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
+- if (!cpu_online(sibling))
+- continue;
+- cpumask_set_cpu(sibling,
+- &this_leaf->shared_cpu_map);
+ }
+ }
+ } else