--- /dev/null
+From d283ee5662c6bf2f3771a36b926f6988e6dddfc6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 23 Jan 2024 11:31:35 +0200
+Subject: drm/i915: Include the PLL name in the debug messages
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit d283ee5662c6bf2f3771a36b926f6988e6dddfc6 upstream.
+
+Make the log easier to parse by including the name of the PLL
+in the debug prints regarding said PLL.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240123093137.9133-1-ville.syrjala@linux.intel.com
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 39 +++++++++++++-------------
+ 1 file changed, 20 insertions(+), 19 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+@@ -4475,25 +4475,25 @@ verify_single_dpll_state(struct drm_i915
+ u8 pipe_mask;
+ bool active;
+
+- drm_dbg_kms(&i915->drm, "%s\n", pll->info->name);
+-
+ active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
+
+ if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
+ I915_STATE_WARN(i915, !pll->on && pll->active_mask,
+- "pll in active use but not on in sw tracking\n");
++ "%s: pll in active use but not on in sw tracking\n",
++ pll->info->name);
+ I915_STATE_WARN(i915, pll->on && !pll->active_mask,
+- "pll is on but not used by any active pipe\n");
++ "%s: pll is on but not used by any active pipe\n",
++ pll->info->name);
+ I915_STATE_WARN(i915, pll->on != active,
+- "pll on state mismatch (expected %i, found %i)\n",
+- pll->on, active);
++ "%s: pll on state mismatch (expected %i, found %i)\n",
++ pll->info->name, pll->on, active);
+ }
+
+ if (!crtc) {
+ I915_STATE_WARN(i915,
+ pll->active_mask & ~pll->state.pipe_mask,
+- "more active pll users than references: 0x%x vs 0x%x\n",
+- pll->active_mask, pll->state.pipe_mask);
++ "%s: more active pll users than references: 0x%x vs 0x%x\n",
++ pll->info->name, pll->active_mask, pll->state.pipe_mask);
+
+ return;
+ }
+@@ -4502,21 +4502,22 @@ verify_single_dpll_state(struct drm_i915
+
+ if (new_crtc_state->hw.active)
+ I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask),
+- "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
+- pipe_name(crtc->pipe), pll->active_mask);
++ "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n",
++ pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
+ else
+ I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
+- "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
+- pipe_name(crtc->pipe), pll->active_mask);
++ "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
++ pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
+
+ I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask),
+- "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
+- pipe_mask, pll->state.pipe_mask);
++ "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
++ pll->info->name, pipe_mask, pll->state.pipe_mask);
+
+ I915_STATE_WARN(i915,
+ pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
+ sizeof(dpll_hw_state)),
+- "pll hw state mismatch\n");
++ "%s: pll hw state mismatch\n",
++ pll->info->name);
+ }
+
+ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
+@@ -4538,11 +4539,11 @@ void intel_shared_dpll_state_verify(stru
+ struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
+
+ I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
+- "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
+- pipe_name(crtc->pipe), pll->active_mask);
++ "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
++ pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
+ I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
+- "pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
+- pipe_name(crtc->pipe), pll->state.pipe_mask);
++ "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
++ pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
+ }
+ }
+
--- /dev/null
+From 92b47c3b8b242a1f1b73d5c1181d5b678ac1382b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Fri, 24 Nov 2023 10:27:32 +0200
+Subject: drm/i915: Replace a memset() with zero initialization
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 92b47c3b8b242a1f1b73d5c1181d5b678ac1382b upstream.
+
+Declaring a struct and immediately zeroing it with memset()
+seems a bit silly to me. Just zero initialize the struct
+when declaring it.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20231124082735.25470-2-ville.syrjala@linux.intel.com
+Reviewed-by: Mika Kahola <mika.kahola@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+@@ -4465,12 +4465,10 @@ verify_single_dpll_state(struct drm_i915
+ struct intel_crtc *crtc,
+ const struct intel_crtc_state *new_crtc_state)
+ {
+- struct intel_dpll_hw_state dpll_hw_state;
++ struct intel_dpll_hw_state dpll_hw_state = {};
+ u8 pipe_mask;
+ bool active;
+
+- memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
+-
+ drm_dbg_kms(&i915->drm, "%s\n", pll->info->name);
+
+ active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
--- /dev/null
+From 33c7760226c79ee8de6c0646640963a8a7ee794a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 23 Jan 2024 11:31:36 +0200
+Subject: drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 33c7760226c79ee8de6c0646640963a8a7ee794a upstream.
+
+TC ports have both the MG/TC and TBT PLLs selected simultanously (so
+that we can switch from MG/TC to TBT as a fallback). This doesn't play
+well with the state checker that assumes that the old PLL shouldn't
+have the pipe in its pipe_mask anymore. Suppress that check for these
+PLLs to avoid spurious WARNs when you disconnect a TC port and a
+non-disabling modeset happens before actually disabling the port.
+
+v2: Only suppress when one of the PLLs is the TBT PLL and the
+ other one is not
+
+Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9816
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240123093137.9133-2-ville.syrjala@linux.intel.com
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++++++++++----
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++++
+ 2 files changed, 23 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+@@ -4029,7 +4029,8 @@ static const struct intel_shared_dpll_fu
+ static const struct dpll_info icl_plls[] = {
+ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
+ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
+- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
++ .flags = INTEL_DPLL_IS_ALT_PORT_DPLL, },
+ { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
+ { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
+ { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
+@@ -4074,7 +4075,8 @@ static const struct intel_shared_dpll_fu
+ static const struct dpll_info tgl_plls[] = {
+ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
+ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
+- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
++ .flags = INTEL_DPLL_IS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
+ { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
+ { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
+@@ -4147,7 +4149,8 @@ static const struct intel_dpll_mgr adls_
+ static const struct dpll_info adlp_plls[] = {
+ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
+ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
+- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
++ .flags = INTEL_DPLL_IS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
+ { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
+ { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
+@@ -4520,6 +4523,14 @@ verify_single_dpll_state(struct drm_i915
+ pll->info->name);
+ }
+
++static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
++ const struct intel_shared_dpll *new_pll)
++{
++ return old_pll && new_pll && old_pll != new_pll &&
++ (old_pll->info->flags & INTEL_DPLL_IS_ALT_PORT_DPLL ||
++ new_pll->info->flags & INTEL_DPLL_IS_ALT_PORT_DPLL);
++}
++
+ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+ {
+@@ -4541,7 +4552,11 @@ void intel_shared_dpll_state_verify(stru
+ I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
+ "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
+ pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
+- I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
++
++ /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
++ I915_STATE_WARN(i915, !has_alt_port_dpll(old_crtc_state->shared_dpll,
++ new_crtc_state->shared_dpll) &&
++ pll->state.pipe_mask & pipe_mask,
+ "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
+ pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
+ }
+--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+@@ -277,12 +277,16 @@ struct dpll_info {
+ enum intel_display_power_domain power_domain;
+
+ #define INTEL_DPLL_ALWAYS_ON (1 << 0)
++#define INTEL_DPLL_IS_ALT_PORT_DPLL (1 << 1)
+ /**
+ * @flags:
+ *
+ * INTEL_DPLL_ALWAYS_ON
+ * Inform the state checker that the DPLL is kept enabled even if
+ * not in use by any CRTC.
++ * INTEL_DPLL_IS_ALT_PORT_DPLL
++ * Inform the state checker that the DPLL can be used as a fallback
++ * (for TC->TBT fallback).
+ */
+ u32 flags;
+ };
--- /dev/null
+From ba407525f8247ee4c270369f3371b9994c27bfda Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 18 Jan 2024 16:24:36 +0200
+Subject: drm/i915: Try to preserve the current shared_dpll for fastset on type-c ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit ba407525f8247ee4c270369f3371b9994c27bfda upstream.
+
+Currently icl_compute_tc_phy_dplls() assumes that the active
+PLL will be the TC PLL (as opposed to the TBT PLL). The actual
+PLL will be selected during the modeset enable sequence, but
+we need to put *something* into the crtc_state->shared_dpll
+already during compute_config().
+
+The downside of assuming one PLL or the other is that we'll
+fail to fastset if the assumption doesn't match what was in
+use previously. So let's instead keep the same PLL that was
+in use previously (assuming there was one). This should allow
+fastset to work again when using TBT PLL, at least in the
+steady state.
+
+Now, assuming we want keep the same PLL may not be entirely
+correct either. But we should be covered by the type-c link
+reset handling which will force a full modeset by flagging
+connectors_changed=true which means the resulting modeset
+can't be converted into a fastset even if the full crtc state
+looks identical.
+
+Cc: Imre Deak <imre.deak@intel.com>
+Cc: Suraj Kandpal <suraj.kandpal@intel.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240118142436.25928-1-ville.syrjala@linux.intel.com
+Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+@@ -3308,6 +3308,8 @@ static int icl_compute_tc_phy_dplls(stru
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
++ const struct intel_crtc_state *old_crtc_state =
++ intel_atomic_get_old_crtc_state(state, crtc);
+ struct icl_port_dpll *port_dpll =
+ &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+ struct skl_wrpll_params pll_params = {};
+@@ -3326,7 +3328,11 @@ static int icl_compute_tc_phy_dplls(stru
+ return ret;
+
+ /* this is mainly for the fastset check */
+- icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
++ if (old_crtc_state->shared_dpll &&
++ old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
++ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
++ else
++ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
+
+ crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
+ &port_dpll->hw_state);
btrfs-do-not-skip-re-registration-for-the-mounted-device.patch
mfd-intel-lpss-switch-to-generalized-quirk-table.patch
mfd-intel-lpss-introduce-quirk_clock_divider_unity-for-xps-9530.patch
+drm-i915-replace-a-memset-with-zero-initialization.patch
+drm-i915-try-to-preserve-the-current-shared_dpll-for-fastset-on-type-c-ports.patch
+drm-i915-include-the-pll-name-in-the-debug-messages.patch
+drm-i915-suppress-old-pll-pipe_mask-checks-for-mg-tc-tbt-plls.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
