/* ... or for a tail-call argument ... */
if (sibling)
{
- gcc_assert (GET_CODE (sibling) == CALL_INSN);
+ gcc_assert (CALL_P (sibling));
if (find_regno_fusage (sibling, USE, 3))
return 0;
cond = NULL_RTX;
if (subtargets || code == SET
- || (GET_CODE (target) == REG && GET_CODE (source) == REG
+ || (REG_P (target) && REG_P (source)
&& REGNO (target) != REGNO (source)))
{
/* After arm_reorg has been called, we can't fix up expensive
if (generate)
{
if (mode == SImode && i == 16)
- /* Use UXTH in preference to UBFX, since on Thumb2 it's a
+ /* Use UXTH in preference to UBFX, since on Thumb2 it's a
smaller insn. */
emit_constant_insn (cond,
gen_zero_extendhisi2
{
/* Missing comparison. First try to use an available
comparison. */
- if (GET_CODE (*op1) == CONST_INT)
+ if (CONST_INT_P (*op1))
{
i = INTVAL (*op1);
switch (code)
/* Comparisons smaller than DImode. Only adjust comparisons against
an out-of-range constant. */
- if (GET_CODE (*op1) != CONST_INT
+ if (!CONST_INT_P (*op1)
|| const_ok_for_arm (INTVAL (*op1))
|| const_ok_for_arm (- INTVAL (*op1)))
return code;
tree index = TYPE_DOMAIN (type);
/* Can't handle incomplete types. */
- if (!COMPLETE_TYPE_P(type))
+ if (!COMPLETE_TYPE_P (type))
return -1;
count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep);
tree field;
/* Can't handle incomplete types. */
- if (!COMPLETE_TYPE_P(type))
+ if (!COMPLETE_TYPE_P (type))
return -1;
for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
tree field;
/* Can't handle incomplete types. */
- if (!COMPLETE_TYPE_P(type))
+ if (!COMPLETE_TYPE_P (type))
return -1;
for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
&& GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC
&& XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS)
{
- gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (XEXP (orig, 0), 1)));
return orig;
}
offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
base == reg ? 0 : reg);
- if (GET_CODE (offset) == CONST_INT)
+ if (CONST_INT_P (offset))
{
/* The base register doesn't really matter, we only want to
test the index for the appropriate mode. */
offset = force_reg (Pmode, offset);
}
- if (GET_CODE (offset) == CONST_INT)
+ if (CONST_INT_P (offset))
return plus_constant (Pmode, base, INTVAL (offset));
}
{
int regno;
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return 0;
regno = REGNO (x);
to fixup invalid register choices. */
if (use_ldrd
&& GET_CODE (x) == POST_MODIFY
- && GET_CODE (addend) == REG)
+ && REG_P (addend))
return 0;
return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
|| (code == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1;
else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
rtx xop1 = XEXP (x, 1);
return ((arm_address_register_rtx_p (xop0, strict_p)
- && ((GET_CODE(xop1) == CONST_INT
+ && ((CONST_INT_P (xop1)
&& arm_legitimate_index_p (mode, xop1, outer, strict_p))
|| (!strict_p && will_be_in_index_register (xop1))))
|| (arm_address_register_rtx_p (xop1, strict_p)
rtx addend = XEXP (XEXP (x, 1), 1);
HOST_WIDE_INT offset;
- if (GET_CODE (addend) != CONST_INT)
+ if (!CONST_INT_P (addend))
return 0;
offset = INTVAL(addend);
|| (code == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1;
else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
rtx op = XEXP (index, 1);
return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
- && GET_CODE (op) == CONST_INT
+ && CONST_INT_P (op)
&& INTVAL (op) > 0
&& INTVAL (op) <= 31);
}
{
HOST_WIDE_INT val;
- if (GET_CODE(op) != CONST_INT)
+ if (!CONST_INT_P (op))
return false;
val = INTVAL(op);
rtx op = XEXP (index, 1);
return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
- && GET_CODE (op) == CONST_INT
+ && CONST_INT_P (op)
&& INTVAL (op) > 0
&& INTVAL (op) <= 3);
}
{
int regno;
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return 0;
regno = REGNO (x);
|| (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1;
/* Post-inc indexing only supported for SImode and larger. */
/* REG+const has 5-7 bit offset for non-SP registers. */
else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
|| XEXP (x, 0) == arg_pointer_rtx)
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
return 1;
larger is supported. */
/* ??? Should probably check for DI/DFmode overflow here
just like GO_IF_LEGITIMATE_OFFSET does. */
- else if (GET_CODE (XEXP (x, 0)) == REG
+ else if (REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode) >= 4
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) >= 0
&& INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
&& (INTVAL (XEXP (x, 1)) & 3) == 0)
return 1;
- else if (GET_CODE (XEXP (x, 0)) == REG
+ else if (REG_P (XEXP (x, 0))
&& (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
|| REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
|| (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
&& REGNO (XEXP (x, 0))
<= LAST_VIRTUAL_POINTER_REGISTER))
&& GET_MODE_SIZE (mode) >= 4
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) & 3) == 0)
return 1;
}
xop1 = force_reg (SImode, xop1);
if (ARM_BASE_REGISTER_RTX_P (xop0)
- && GET_CODE (xop1) == CONST_INT)
+ && CONST_INT_P (xop1))
{
HOST_WIDE_INT n, low_n;
rtx base_reg, val;
with absolute addresses which often allows for the base register to
be factorized for multiple adjacent memory references, and it might
even allows for the mini pool to be avoided entirely. */
- else if (GET_CODE (x) == CONST_INT && optimize > 0)
+ else if (CONST_INT_P (x) && optimize > 0)
{
unsigned int bits;
HOST_WIDE_INT mask, base, index;
return legitimize_tls_address (x, NULL_RTX);
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
|| INTVAL (XEXP (x, 1)) < 0))
{
/* We must recognize output that we have already generated ourselves. */
if (GET_CODE (*p) == PLUS
&& GET_CODE (XEXP (*p, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (*p, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (*p, 0), 1)) == CONST_INT
- && GET_CODE (XEXP (*p, 1)) == CONST_INT)
+ && REG_P (XEXP (XEXP (*p, 0), 0))
+ && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
+ && CONST_INT_P (XEXP (*p, 1)))
{
push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
}
if (GET_CODE (*p) == PLUS
- && GET_CODE (XEXP (*p, 0)) == REG
+ && REG_P (XEXP (*p, 0))
&& ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0)))
/* If the base register is equivalent to a constant, let the generic
code handle it. Otherwise we will run into problems if a future
reload pass decides to rematerialize the constant. */
&& !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p, 0)))
- && GET_CODE (XEXP (*p, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (*p, 1)))
{
HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
HOST_WIDE_INT low, high;
&& GET_MODE_SIZE (mode) < 4
&& REG_P (XEXP (x, 0))
&& XEXP (x, 0) == stack_pointer_rtx
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
{
rtx orig_x = x;
static bool
thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
- return (GET_CODE (x) == CONST_INT
- || GET_CODE (x) == CONST_DOUBLE
+ return (CONST_INT_P (x)
+ || CONST_DOUBLE_P (x)
|| CONSTANT_ADDRESS_P (x)
|| flag_pic);
}
}
\f
#define REG_OR_SUBREG_REG(X) \
- (GET_CODE (X) == REG \
- || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
+ (REG_P (X) \
+ || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))))
#define REG_OR_SUBREG_RTX(X) \
- (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
+ (REG_P (X) ? (X) : SUBREG_REG (X))
static inline int
thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
return COSTS_N_INSNS (1);
case MULT:
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
int cycles = 0;
unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
case SET:
return (COSTS_N_INSNS (1)
- + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
- + GET_CODE (SET_DEST (x)) == MEM));
+ + 4 * ((MEM_P (SET_SRC (x)))
+ + MEM_P (SET_DEST (x))));
case CONST_INT:
if (outer == SET)
return false;
case ROTATE:
- if (GET_CODE (XEXP (x, 1)) == REG)
+ if (REG_P (XEXP (x, 1)))
*total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
- else if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ else if (!CONST_INT_P (XEXP (x, 1)))
*total = rtx_cost (XEXP (x, 1), code, 1, speed);
/* Fall through */
/* Increase the cost of complex shifts because they aren't any faster,
and reduce dual issue opportunities. */
if (arm_tune_cortex_a9
- && outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT)
+ && outer != SET && !CONST_INT_P (XEXP (x, 1)))
++*total;
return true;
if (mode == DImode)
{
*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
- if (GET_CODE (XEXP (x, 0)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 0))
&& const_ok_for_arm (INTVAL (XEXP (x, 0))))
{
*total += rtx_cost (XEXP (x, 1), code, 1, speed);
return true;
}
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_arm (INTVAL (XEXP (x, 1))))
{
*total += rtx_cost (XEXP (x, 0), code, 0, speed);
|| (mode == DFmode && !TARGET_VFP_SINGLE)))
{
*total = COSTS_N_INSNS (1);
- if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (XEXP (x, 0))
&& arm_const_double_rtx (XEXP (x, 0)))
{
*total += rtx_cost (XEXP (x, 1), code, 1, speed);
return true;
}
- if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (XEXP (x, 1))
&& arm_const_double_rtx (XEXP (x, 1)))
{
*total += rtx_cost (XEXP (x, 0), code, 0, speed);
}
*total = COSTS_N_INSNS (1);
- if (GET_CODE (XEXP (x, 0)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 0))
&& const_ok_for_arm (INTVAL (XEXP (x, 0))))
{
*total += rtx_cost (XEXP (x, 1), code, 1, speed);
|| GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE)
{
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
- if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
+ if (REG_P (XEXP (XEXP (x, 1), 0))
&& REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM)
*total += COSTS_N_INSNS (1);
|| (mode == DFmode && !TARGET_VFP_SINGLE)))
{
*total = COSTS_N_INSNS (1);
- if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (XEXP (x, 1))
&& arm_const_double_rtx (XEXP (x, 1)))
{
*total += rtx_cost (XEXP (x, 0), code, 0, speed);
|| GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE)
{
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, 1, speed);
- if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ if (REG_P (XEXP (XEXP (x, 0), 0))
&& REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM)
*total += COSTS_N_INSNS (1);
return true;
operand. */
if (REG_OR_SUBREG_REG (XEXP (x, 0))
&& ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
- && GET_CODE (XEXP (x, 1)) != CONST_INT)
+ && !CONST_INT_P (XEXP (x, 1)))
*total = COSTS_N_INSNS (1);
if (mode == DImode)
{
*total += COSTS_N_INSNS (2);
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_op (INTVAL (XEXP (x, 1)), code))
{
*total += rtx_cost (XEXP (x, 0), code, 0, speed);
}
*total += COSTS_N_INSNS (1);
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_op (INTVAL (XEXP (x, 1)), code))
{
*total += rtx_cost (XEXP (x, 0), code, 0, speed);
{
*total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
/* Register shifts cost an extra cycle. */
- if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (XEXP (x, 0), 1)))
*total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1),
subcode, 1, speed);
return true;
if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE
|| GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE)
- && GET_CODE (XEXP (operand, 0)) == REG
+ && REG_P (XEXP (operand, 0))
&& REGNO (XEXP (operand, 0)) == CC_REGNUM))
*total += COSTS_N_INSNS (1);
*total += (rtx_cost (XEXP (x, 1), code, 1, speed)
goto scc_insn;
case GE:
- if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM)
+ if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
&& mode == SImode && XEXP (x, 1) == const0_rtx)
{
*total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
goto scc_insn;
case LT:
- if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM)
+ if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
&& mode == SImode && XEXP (x, 1) == const0_rtx)
{
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
performed, then they cost 2 instructions. Otherwise they need
an additional comparison before them. */
*total = COSTS_N_INSNS (2);
- if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM)
+ if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
{
return true;
}
/* Fall through */
case COMPARE:
- if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM)
+ if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
{
*total = 0;
return true;
}
*total += COSTS_N_INSNS (1);
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_op (INTVAL (XEXP (x, 1)), code))
{
*total += rtx_cost (XEXP (x, 0), code, 0, speed);
case SMIN:
case SMAX:
*total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
- if (GET_CODE (XEXP (x, 1)) != CONST_INT
+ if (!CONST_INT_P (XEXP (x, 1))
|| !const_ok_for_arm (INTVAL (XEXP (x, 1))))
*total += rtx_cost (XEXP (x, 1), code, 1, speed);
return true;
case SET:
return false;
-
+
case UNSPEC:
/* We cost this as high as our memory costs to allow this to
be hoisted from loops. */
return COSTS_N_INSNS (1);
case MULT:
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
/* Thumb1 mul instruction can't operate on const. We must Load it
into a register first. */
case SET:
return (COSTS_N_INSNS (1)
- + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
- + GET_CODE (SET_DEST (x)) == MEM));
+ + 4 * ((MEM_P (SET_SRC (x)))
+ + MEM_P (SET_DEST (x))));
case CONST_INT:
if (outer == SET)
{
case QImode:
return (1 + (mode == DImode ? 4 : 0)
- + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
+ + (MEM_P (XEXP (x, 0)) ? 10 : 0));
case HImode:
return (4 + (mode == DImode ? 4 : 0)
- + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
+ + (MEM_P (XEXP (x, 0)) ? 10 : 0));
case SImode:
- return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
+ return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
default:
return 99;
return false;
case ROTATE:
- if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
+ if (mode == SImode && REG_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, false);
return true;
case ASHIFT:
case LSHIFTRT:
case ASHIFTRT:
- if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (mode == DImode && CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, 0, false);
return true;
{
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, false);
/* Slightly disparage register shifts, but not by much. */
- if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (x, 1)))
*total += 1 + rtx_cost (XEXP (x, 1), code, 1, false);
return true;
}
return false;
}
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
& (unsigned HOST_WIDE_INT) 0xffffffff);
return false;
}
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
& (unsigned HOST_WIDE_INT) 0xffffffff);
return false;
}
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
/* If operand 1 is a constant we can more accurately
calculate the cost of the multiply. The multiplier can
if (c == PLUS)
{
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
return 2;
if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
if (c == REG)
return 1;
if (c == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ && REG_P (XEXP (x, 0))
+ && CONST_INT_P (XEXP (x, 1)))
return 1;
return 2;
/* Call insns don't incur a stall, even if they follow a load. */
if (REG_NOTE_KIND (link) == 0
- && GET_CODE (insn) == CALL_INSN)
+ && CALL_P (insn))
return 1;
if ((i_pat = single_set (insn)) != NULL
- && GET_CODE (SET_SRC (i_pat)) == MEM
+ && MEM_P (SET_SRC (i_pat))
&& (d_pat = single_set (dep)) != NULL
- && GET_CODE (SET_DEST (d_pat)) == MEM)
+ && MEM_P (SET_DEST (d_pat)))
{
rtx src_mem = XEXP (SET_SRC (i_pat), 0);
/* This is a load after a store, there is no conflict if the load reads
HOST_WIDE_INT m1, m2;
int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
- if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE)
+ if (!TARGET_VFP3 || !CONST_DOUBLE_P (x))
return -1;
REAL_VALUE_FROM_CONST_DOUBLE (r, x);
unsigned HOST_WIDE_INT elpart;
unsigned int part, parts;
- if (GET_CODE (el) == CONST_INT)
+ if (CONST_INT_P (el))
{
elpart = INTVAL (el);
parts = 1;
}
- else if (GET_CODE (el) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (el))
{
elpart = CONST_DOUBLE_LOW (el);
parts = 2;
bytes[idx++] = (elpart & 0xff) ^ invmask;
elpart >>= BITS_PER_UNIT;
}
- if (GET_CODE (el) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (el))
elpart = CONST_DOUBLE_HIGH (el);
}
}
rtx el = CONST_VECTOR_ELT (op, i);
unsigned HOST_WIDE_INT elpart;
- if (GET_CODE (el) == CONST_INT)
+ if (CONST_INT_P (el))
elpart = INTVAL (el);
- else if (GET_CODE (el) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (el))
return 0;
else
gcc_unreachable ();
for (i = 0; i < n_elts; ++i)
{
rtx x = XVECEXP (vals, 0, i);
- if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
n_const++;
}
if (n_const == n_elts)
{
HOST_WIDE_INT lane;
- gcc_assert (GET_CODE (operand) == CONST_INT);
+ gcc_assert (CONST_INT_P (operand));
lane = INTVAL (operand);
return FALSE;
/* Constants are converted into offsets from labels. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
ind = XEXP (op, 0);
|| (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE;
/* Match: (mem (reg)). */
- if (GET_CODE (ind) == REG)
+ if (REG_P (ind))
return arm_address_register_rtx_p (ind, 0);
/* Autoincremment addressing modes. POST_INC and PRE_DEC are
(plus (reg)
(const)). */
if (GET_CODE (ind) == PLUS
- && GET_CODE (XEXP (ind, 0)) == REG
+ && REG_P (XEXP (ind, 0))
&& REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
- && GET_CODE (XEXP (ind, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (ind, 1))
&& INTVAL (XEXP (ind, 1)) > -1024
&& INTVAL (XEXP (ind, 1)) < 1024
&& (INTVAL (XEXP (ind, 1)) & 3) == 0)
return FALSE;
/* Constants are converted into offsets from labels. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
ind = XEXP (op, 0);
|| (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE;
/* Match: (mem (reg)). */
- if (GET_CODE (ind) == REG)
+ if (REG_P (ind))
return arm_address_register_rtx_p (ind, 0);
/* Allow post-increment with Neon registers. */
(const)). */
if (type == 0
&& GET_CODE (ind) == PLUS
- && GET_CODE (XEXP (ind, 0)) == REG
+ && REG_P (XEXP (ind, 0))
&& REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
- && GET_CODE (XEXP (ind, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (ind, 1))
&& INTVAL (XEXP (ind, 1)) > -1024
&& INTVAL (XEXP (ind, 1)) < 1016
&& (INTVAL (XEXP (ind, 1)) & 3) == 0)
return FALSE;
/* Constants are converted into offsets from labels. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
ind = XEXP (op, 0);
|| (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE;
/* Match: (mem (reg)). */
- if (GET_CODE (ind) == REG)
+ if (REG_P (ind))
return arm_address_register_rtx_p (ind, 0);
/* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
if (volatile_refs_p (a) || volatile_refs_p (b))
return 0;
- if ((GET_CODE (XEXP (a, 0)) == REG
+ if ((REG_P (XEXP (a, 0))
|| (GET_CODE (XEXP (a, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
- && (GET_CODE (XEXP (b, 0)) == REG
+ && CONST_INT_P (XEXP (XEXP (a, 0), 1))))
+ && (REG_P (XEXP (b, 0))
|| (GET_CODE (XEXP (b, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (b, 0), 1)))))
{
HOST_WIDE_INT val0 = 0, val1 = 0;
rtx reg0, reg1;
if (GET_CODE (operands[nops + i]) == SUBREG)
operands[nops + i] = alter_subreg (operands + (nops + i));
- gcc_assert (GET_CODE (operands[nops + i]) == MEM);
+ gcc_assert (MEM_P (operands[nops + i]));
/* Don't reorder volatile memory references; it doesn't seem worth
looking for the case where the order is ok anyway. */
offset = const0_rtx;
- if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
+ if ((REG_P (reg = XEXP (operands[nops + i], 0))
|| (GET_CODE (reg) == SUBREG
- && GET_CODE (reg = SUBREG_REG (reg)) == REG))
+ && REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
- && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
- == REG)
+ && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
|| (GET_CODE (reg) == SUBREG
- && GET_CODE (reg = SUBREG_REG (reg)) == REG))
- && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
- == CONST_INT)))
+ && REG_P (reg = SUBREG_REG (reg))))
+ && (CONST_INT_P (offset
+ = XEXP (XEXP (operands[nops + i], 0), 1)))))
{
if (i == 0)
{
/* Not addressed from the same base register. */
return 0;
- unsorted_regs[i] = (GET_CODE (operands[i]) == REG
+ unsorted_regs[i] = (REG_P (operands[i])
? REGNO (operands[i])
: REGNO (SUBREG_REG (operands[i])));
if (GET_CODE (operands[nops + i]) == SUBREG)
operands[nops + i] = alter_subreg (operands + (nops + i));
- gcc_assert (GET_CODE (operands[nops + i]) == MEM);
+ gcc_assert (MEM_P (operands[nops + i]));
/* Don't reorder volatile memory references; it doesn't seem worth
looking for the case where the order is ok anyway. */
offset = const0_rtx;
- if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
+ if ((REG_P (reg = XEXP (operands[nops + i], 0))
|| (GET_CODE (reg) == SUBREG
- && GET_CODE (reg = SUBREG_REG (reg)) == REG))
+ && REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
- && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
- == REG)
+ && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
|| (GET_CODE (reg) == SUBREG
- && GET_CODE (reg = SUBREG_REG (reg)) == REG))
- && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
- == CONST_INT)))
+ && REG_P (reg = SUBREG_REG (reg))))
+ && (CONST_INT_P (offset
+ = XEXP (XEXP (operands[nops + i], 0), 1)))))
{
- unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG
+ unsorted_reg_rtxs[i] = (REG_P (operands[i])
? operands[i] : SUBREG_REG (operands[i]));
unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]);
unaligned copies on processors which support unaligned semantics for those
instructions. INTERLEAVE_FACTOR can be used to attempt to hide load latency
(using more registers) by doing e.g. load/load/store/store for a factor of 2.
- An interleave factor of 1 (the minimum) will perform no interleaving.
+ An interleave factor of 1 (the minimum) will perform no interleaving.
Load/store multiple are used for aligned addresses where possible. */
static void
rtx part_bytes_reg = NULL;
rtx mem;
- if (GET_CODE (operands[2]) != CONST_INT
- || GET_CODE (operands[3]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
+ || !CONST_INT_P (operands[3])
|| INTVAL (operands[2]) > 64)
return 0;
equalities and unsigned inequalities). */
if (GET_MODE (x) == SImode
&& GET_CODE (x) == ASHIFT
- && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
+ && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 24
&& GET_CODE (XEXP (x, 0)) == SUBREG
- && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
+ && MEM_P (SUBREG_REG (XEXP (x, 0)))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
&& (op == EQ || op == NE
|| op == GEU || op == GTU || op == LTU || op == LEU)
- && GET_CODE (y) == CONST_INT)
+ && CONST_INT_P (y))
return CC_Zmode;
/* A construct for a conditional compare, if the false arm contains
ref = SUBREG_REG (ref);
}
- if (GET_CODE (ref) == REG)
+ if (REG_P (ref))
{
/* We have a pseudo which has been spilt onto the stack; there
are two cases here: the first where there is a simple
/* Handle the case where the address is too complex to be offset by 1. */
if (GET_CODE (base) == MINUS
- || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
+ || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1))))
{
rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
ref = SUBREG_REG (ref);
}
- if (GET_CODE (ref) == REG)
+ if (REG_P (ref))
{
/* We have a pseudo which has been spilt onto the stack; there
are two cases here: the first where there is a simple
/* Handle the case where the address is too complex to be offset by 1. */
if (GET_CODE (base) == MINUS
- || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
+ || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1))))
{
rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
&& ((table = next_real_insn (JUMP_LABEL (insn)))
== next_real_insn (insn))
&& table != NULL
- && GET_CODE (table) == JUMP_INSN
+ && JUMP_P (table)
&& (GET_CODE (PATTERN (table)) == ADDR_VEC
|| GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
return table;
{
if (GET_CODE (fix->value) == GET_CODE (mp->value)
&& fix->mode == mp->mode
- && (GET_CODE (fix->value) != CODE_LABEL
+ && (!LABEL_P (fix->value)
|| (CODE_LABEL_NUMBER (fix->value)
== CODE_LABEL_NUMBER (mp->value)))
&& rtx_equal_p (fix->value, mp->value))
{
if (GET_CODE (fix->value) == GET_CODE (mp->value)
&& fix->mode == mp->mode
- && (GET_CODE (fix->value) != CODE_LABEL
+ && (!LABEL_P (fix->value)
|| (CODE_LABEL_NUMBER (fix->value)
== CODE_LABEL_NUMBER (mp->value)))
&& rtx_equal_p (fix->value, mp->value)
int base_cost = 50;
rtx next = next_nonnote_insn (insn);
- if (next != NULL && GET_CODE (next) == CODE_LABEL)
+ if (next != NULL && LABEL_P (next))
base_cost -= 20;
switch (GET_CODE (insn))
/* This code shouldn't have been called if there was a natural barrier
within range. */
- gcc_assert (GET_CODE (from) != BARRIER);
+ gcc_assert (!BARRIER_P (from));
/* Count the length of this insn. This must stay in sync with the
code that pushes minipool fixes. */
lowpart = gen_lowpart (SImode, val);
highpart = gen_highpart_mode (SImode, mode, val);
- gcc_assert (GET_CODE (lowpart) == CONST_INT);
- gcc_assert (GET_CODE (highpart) == CONST_INT);
+ gcc_assert (CONST_INT_P (lowpart));
+ gcc_assert (CONST_INT_P (highpart));
return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
NULL_RTX, NULL_RTX, 0, 0)
part = gen_highpart_mode (SImode, mode, val);
- gcc_assert (GET_CODE (part) == CONST_INT);
+ gcc_assert (CONST_INT_P (part));
if (const_ok_for_arm (INTVAL (part))
|| const_ok_for_arm (~INTVAL (part)))
part = gen_lowpart (SImode, val);
- gcc_assert (GET_CODE (part) == CONST_INT);
+ gcc_assert (CONST_INT_P (part));
if (const_ok_for_arm (INTVAL (part))
|| const_ok_for_arm (~INTVAL (part)))
part = gen_highpart_mode (SImode, mode, val);
- gcc_assert (GET_CODE (part) == CONST_INT);
+ gcc_assert (CONST_INT_P (part));
if (!const_ok_for_arm (INTVAL (part)))
return false;
part = gen_lowpart (SImode, val);
- gcc_assert (GET_CODE (part) == CONST_INT);
+ gcc_assert (CONST_INT_P (part));
if (!const_ok_for_arm (INTVAL (part)))
return false;
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno], op);
}
- else if (GET_CODE (op) == MEM
+ else if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
{
break;
case MINUS:
- /* RSBS <Rd>,<Rn>,#0
+ /* RSBS <Rd>,<Rn>,#0
Not handled here: see NEG below. */
/* SUBS <Rd>,<Rn>,#<imm3>
SUBS <Rdn>,#<imm8>
/* The first insn must always be a note, or the code below won't
scan it properly. */
insn = get_insns ();
- gcc_assert (GET_CODE (insn) == NOTE);
+ gcc_assert (NOTE_P (insn));
minipool_pad = 0;
/* Scan all the insns and record the operands that will need fixing. */
for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
{
- if (GET_CODE (insn) == BARRIER)
+ if (BARRIER_P (insn))
push_minipool_barrier (insn, address);
else if (INSN_P (insn))
{
Mfix * this_fix;
/* Skip any further barriers before the next fix. */
- while (fix && GET_CODE (fix->insn) == BARRIER)
+ while (fix && BARRIER_P (fix->insn))
fix = fix->next;
/* No more fixes. */
for (ftmp = fix; ftmp; ftmp = ftmp->next)
{
- if (GET_CODE (ftmp->insn) == BARRIER)
+ if (BARRIER_P (ftmp->insn))
{
if (ftmp->address >= minipool_vector_head->max_address)
break;
while (ftmp)
{
- if (GET_CODE (ftmp->insn) != BARRIER
+ if (!BARRIER_P (ftmp->insn)
&& ((ftmp->minipool = add_minipool_backward_ref (ftmp))
== NULL))
break;
up and adding the constants to the pool itself. */
for (this_fix = fix; this_fix && ftmp != this_fix;
this_fix = this_fix->next)
- if (GET_CODE (this_fix->insn) != BARRIER)
+ if (!BARRIER_P (this_fix->insn))
{
rtx addr
= plus_constant (Pmode,
strcpy (pattern, "fstmfdd%?\t%m0!, {%P1");
p = strlen (pattern);
- gcc_assert (GET_CODE (operands[1]) == REG);
+ gcc_assert (REG_P (operands[1]));
base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
for (i = 1; i < XVECLEN (operands[2], 0); i++)
FIXME: IWMMXT allows offsets larger than ldrd can
handle, fix these up with a pair of ldr. */
if (TARGET_THUMB2
- || GET_CODE (otherops[2]) != CONST_INT
+ || !CONST_INT_P (otherops[2])
|| (INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256))
{
FIXME: IWMMXT allows offsets larger than ldrd can handle,
fix these up with a pair of ldr. */
if (TARGET_THUMB2
- || GET_CODE (otherops[2]) != CONST_INT
+ || !CONST_INT_P (otherops[2])
|| (INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256))
{
if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
{
- if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
+ if (CONST_INT_P (otherops[2]) && !TARGET_LDRD)
{
switch ((int) INTVAL (otherops[2]))
{
otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1);
operands[1] = otherops[0];
if (TARGET_LDRD
- && (GET_CODE (otherops[2]) == REG
+ && (REG_P (otherops[2])
|| TARGET_THUMB2
- || (GET_CODE (otherops[2]) == CONST_INT
+ || (CONST_INT_P (otherops[2])
&& INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256)))
{
return "";
}
- if (GET_CODE (otherops[2]) == CONST_INT)
+ if (CONST_INT_P (otherops[2]))
{
if (emit)
{
/* IWMMXT allows offsets larger than ldrd can handle,
fix these up with a pair of ldr. */
if (!TARGET_THUMB2
- && GET_CODE (otherops[2]) == CONST_INT
+ && CONST_INT_P (otherops[2])
&& (INTVAL(otherops[2]) <= -256
|| INTVAL(otherops[2]) >= 256))
{
case PLUS:
otherops[2] = XEXP (XEXP (operands[0], 0), 1);
- if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
+ if (CONST_INT_P (otherops[2]) && !TARGET_LDRD)
{
switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
{
}
}
if (TARGET_LDRD
- && (GET_CODE (otherops[2]) == REG
+ && (REG_P (otherops[2])
|| TARGET_THUMB2
- || (GET_CODE (otherops[2]) == CONST_INT
+ || (CONST_INT_P (otherops[2])
&& INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256)))
{
addr = XEXP (mem, 0);
- if (GET_CODE (addr) == REG
+ if (REG_P (addr)
|| (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
- && GET_CODE (XEXP (addr, 1)) == CONST_INT))
+ && REG_P (XEXP (addr, 0))
+ && CONST_INT_P (XEXP (addr, 1))))
return 1;
else
return 0;
return;
case 'B':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
{
HOST_WIDE_INT val;
val = ARM_SIGN_EXTEND (~INTVAL (x));
The 'Q' and 'R' constraints are also available for 64-bit
constants. */
case 'Q':
- if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
{
rtx part = gen_lowpart (SImode, x);
fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
return;
}
- if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
return;
case 'R':
- if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
{
enum machine_mode mode = GET_MODE (x);
rtx part;
return;
}
- if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
return;
case 'H':
- if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
return;
case 'J':
- if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
return;
case 'K':
- if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
case 'm':
asm_fprintf (stream, "%r",
- GET_CODE (XEXP (x, 0)) == REG
+ REG_P (XEXP (x, 0))
? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
return;
return;
case 'U':
- if (GET_CODE (x) != REG
+ if (!REG_P (x)
|| REGNO (x) < FIRST_IWMMXT_GR_REGNUM
|| REGNO (x) > LAST_IWMMXT_GR_REGNUM)
/* Bad value for wCG register number. */
/* Print an iWMMXt control register name. */
case 'w':
- if (GET_CODE (x) != CONST_INT
+ if (!CONST_INT_P (x)
|| INTVAL (x) < 0
|| INTVAL (x) >= 16)
/* Bad value for wC register number. */
int mode = GET_MODE (x);
int regno;
- if (GET_MODE_SIZE (mode) != 8 || GET_CODE (x) != REG)
+ if (GET_MODE_SIZE (mode) != 8 || !REG_P (x))
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
return;
}
- if (GET_CODE (x) != REG
+ if (!REG_P (x)
|| !IS_VFP_REGNUM (REGNO (x)))
{
output_operand_lossage ("invalid operand for code '%c'", code);
int regno;
if ((GET_MODE_SIZE (mode) != 16
- && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG)
+ && GET_MODE_SIZE (mode) != 32) || !REG_P (x))
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
bool postinc = FALSE;
unsigned align, memsize, align_bits;
- gcc_assert (GET_CODE (x) == MEM);
+ gcc_assert (MEM_P (x));
addr = XEXP (x, 0);
if (GET_CODE (addr) == POST_INC)
{
{
rtx addr;
- gcc_assert (GET_CODE (x) == MEM);
+ gcc_assert (MEM_P (x));
addr = XEXP (x, 0);
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
asm_fprintf (stream, "[%r]", REGNO (addr));
}
return;
int mode = GET_MODE (x);
int regno;
- if (GET_MODE_SIZE (mode) != 4 || GET_CODE (x) != REG)
+ if (GET_MODE_SIZE (mode) != 4 || !REG_P (x))
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
return;
case 'v':
- gcc_assert (GET_CODE (x) == CONST_DOUBLE);
+ gcc_assert (CONST_DOUBLE_P (x));
fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x));
return;
int mode = GET_MODE (x);
int regno;
- if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG)
+ if (GET_MODE_SIZE (mode) != 2 || !REG_P (x))
{
output_operand_lossage ("invalid operand for code '%c'", code);
return;
{
int is_minus = GET_CODE (x) == MINUS;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
asm_fprintf (stream, "[%r]", REGNO (x));
else if (GET_CODE (x) == PLUS || is_minus)
{
rtx base = XEXP (x, 0);
rtx index = XEXP (x, 1);
HOST_WIDE_INT offset = 0;
- if (GET_CODE (base) != REG
- || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM))
+ if (!REG_P (base)
+ || (REG_P (index) && REGNO (index) == SP_REGNUM))
{
/* Ensure that BASE is a register. */
/* (one of them must be). */
{
extern enum machine_mode output_memory_reference_mode;
- gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
+ gcc_assert (REG_P (XEXP (x, 0)));
if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC)
asm_fprintf (stream, "[%r, #%s%d]!",
else if (GET_CODE (x) == PRE_MODIFY)
{
asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0)));
- if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (XEXP (x, 1), 1)))
asm_fprintf (stream, "#%wd]!",
INTVAL (XEXP (XEXP (x, 1), 1)));
else
else if (GET_CODE (x) == POST_MODIFY)
{
asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0)));
- if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (XEXP (x, 1), 1)))
asm_fprintf (stream, "#%wd",
INTVAL (XEXP (XEXP (x, 1), 1)));
else
}
else
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
asm_fprintf (stream, "[%r]", REGNO (x));
else if (GET_CODE (x) == POST_INC)
asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0)));
else if (GET_CODE (x) == PLUS)
{
- gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ gcc_assert (REG_P (XEXP (x, 0)));
+ if (CONST_INT_P (XEXP (x, 1)))
asm_fprintf (stream, "[%r, #%wd]",
REGNO (XEXP (x, 0)),
INTVAL (XEXP (x, 1)));
return;
/* Conditional jumps are implemented directly. */
- if (GET_CODE (insn) == JUMP_INSN)
+ if (JUMP_P (insn))
return;
predicate = COND_EXEC_TEST (body);
/* Jumping into the middle of an IT block is illegal, so a label or
barrier terminates the block. */
- if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
+ if (!NONJUMP_INSN_P (insn) && !JUMP_P (insn))
break;
body = PATTERN (insn);
arm_condexec_masklen += n;
/* A jump must be the last instruction in a conditional block. */
- if (GET_CODE(insn) == JUMP_INSN)
+ if (JUMP_P (insn))
break;
}
/* Restore recog_data (getting the attributes of other insns can
if (simplejump_p (insn))
{
start_insn = next_nonnote_insn (start_insn);
- if (GET_CODE (start_insn) == BARRIER)
+ if (BARRIER_P (start_insn))
{
/* XXX Isn't this always a barrier? */
start_insn = next_nonnote_insn (start_insn);
}
- if (GET_CODE (start_insn) == CODE_LABEL
+ if (LABEL_P (start_insn)
&& CODE_LABEL_NUMBER (start_insn) == arm_target_label
&& LABEL_NUSES (start_insn) == 1)
reverse = TRUE;
else if (ANY_RETURN_P (body))
{
start_insn = next_nonnote_insn (start_insn);
- if (GET_CODE (start_insn) == BARRIER)
+ if (BARRIER_P (start_insn))
start_insn = next_nonnote_insn (start_insn);
- if (GET_CODE (start_insn) == CODE_LABEL
+ if (LABEL_P (start_insn)
&& CODE_LABEL_NUMBER (start_insn) == arm_target_label
&& LABEL_NUSES (start_insn) == 1)
{
}
gcc_assert (!arm_ccfsm_state || reverse);
- if (GET_CODE (insn) != JUMP_INSN)
+ if (!JUMP_P (insn))
return;
/* This jump might be paralleled with a clobber of the condition codes
if the following two insns are a barrier and the
target label. */
this_insn = next_nonnote_insn (this_insn);
- if (this_insn && GET_CODE (this_insn) == BARRIER)
+ if (this_insn && BARRIER_P (this_insn))
this_insn = next_nonnote_insn (this_insn);
if (this_insn && this_insn == label
{
this_insn = next_nonnote_insn (this_insn);
gcc_assert (!this_insn
- || (GET_CODE (this_insn) != BARRIER
- && GET_CODE (this_insn) != CODE_LABEL));
+ || (!BARRIER_P (this_insn)
+ && !LABEL_P (this_insn)));
}
if (!this_insn)
{
return 0;
/* We can only cope with the case where the address is held in a register. */
- if (GET_CODE (addr) != REG)
+ if (!REG_P (addr))
return 0;
/* If we are using the frame pointer to point at the argument, then
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
- if ( GET_CODE (insn) == INSN
+ if ( NONJUMP_INSN_P (insn)
&& GET_CODE (PATTERN (insn)) == SET
&& REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
&& GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
- && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
+ && REG_P (XEXP (XEXP (PATTERN (insn), 1), 0))
&& REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
- && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (PATTERN (insn), 1), 1))
)
{
value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
op0 = expand_normal (arg0);
op1 = expand_normal (arg1);
op2 = expand_normal (arg2);
- if (GET_CODE (op2) == CONST_INT)
+ if (CONST_INT_P (op2))
{
icode = CODE_FOR_iwmmxt_waligni;
tmode = insn_data[icode].operand[0].mode;
insn with the far jump attribute set. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
- if (GET_CODE (insn) == JUMP_INSN
+ if (JUMP_P (insn)
/* Ignore tablejump patterns. */
&& GET_CODE (PATTERN (insn)) != ADDR_VEC
&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
const char * name;
FILE *f = asm_out_file;
- gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
+ gcc_assert (MEM_P (DECL_RTL (current_function_decl)));
gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
== SYMBOL_REF);
name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
rtx arg1;
rtx arg2;
- gcc_assert (GET_CODE (operands[0]) == REG);
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (REG_P (operands[0]));
+ gcc_assert (MEM_P (operands[1]));
/* Get the memory address. */
addr = XEXP (operands[1], 0);
else
base = arg1, offset = arg2;
- gcc_assert (GET_CODE (base) == REG);
+ gcc_assert (REG_P (base));
/* Catch the case of <address> = <reg> + <reg> */
- if (GET_CODE (offset) == REG)
+ if (REG_P (offset))
{
int reg_offset = REGNO (offset);
int reg_base = REGNO (base);
rtx wcgr;
rtx sum;
- if (GET_CODE (operands [1]) != MEM
+ if (!MEM_P (operands [1])
|| GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
- || GET_CODE (reg = XEXP (sum, 0)) != REG
- || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
+ || !REG_P (reg = XEXP (sum, 0))
+ || !CONST_INT_P (offset = XEXP (sum, 1))
|| ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
return "wldrw%?\t%0, %1";
/* This is either an actual independent shift, or a shift applied to
the first operand of another operation. We want the whole shift
operation. */
- if (GET_CODE (early_op) == REG)
+ if (REG_P (early_op))
early_op = op;
return !reg_overlap_mentioned_p (value, early_op);
/* This is either an actual independent shift, or a shift applied to
the first operand of another operation. We want the value being
shifted, in either case. */
- if (GET_CODE (early_op) != REG)
+ if (!REG_P (early_op))
early_op = XEXP (early_op, 0);
return !reg_overlap_mentioned_p (value, early_op);
/* First insn will adjust the stack pointer. */
if (GET_CODE (e) != SET
- || GET_CODE (XEXP (e, 0)) != REG
+ || !REG_P (XEXP (e, 0))
|| REGNO (XEXP (e, 0)) != SP_REGNUM
|| GET_CODE (XEXP (e, 1)) != PLUS)
abort ();
Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
e = XVECEXP (p, 0, i);
if (GET_CODE (e) != SET
- || GET_CODE (XEXP (e, 0)) != MEM
- || GET_CODE (XEXP (e, 1)) != REG)
+ || !MEM_P (XEXP (e, 0))
+ || !REG_P (XEXP (e, 1)))
abort ();
reg = REGNO (XEXP (e, 1));
if (GET_CODE (e) == PLUS)
{
offset += reg_size;
- if (GET_CODE (XEXP (e, 0)) != REG
+ if (!REG_P (XEXP (e, 0))
|| REGNO (XEXP (e, 0)) != SP_REGNUM
- || GET_CODE (XEXP (e, 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (e, 1))
|| offset != INTVAL (XEXP (e, 1)))
abort ();
}
else if (i != 1
- || GET_CODE (e) != REG
+ || !REG_P (e)
|| REGNO (e) != SP_REGNUM)
abort ();
#endif
case MEM:
/* Pushing a single register. */
if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
- || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
+ || !REG_P (XEXP (XEXP (e0, 0), 0))
|| REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
abort ();
{
/* A stack increment. */
if (GET_CODE (e1) != PLUS
- || GET_CODE (XEXP (e1, 0)) != REG
+ || !REG_P (XEXP (e1, 0))
|| REGNO (XEXP (e1, 0)) != SP_REGNUM
- || GET_CODE (XEXP (e1, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (e1, 1)))
abort ();
asm_fprintf (asm_out_file, "\t.pad #%wd\n",
if (GET_CODE (e1) == PLUS)
{
- if (GET_CODE (XEXP (e1, 0)) != REG
- || GET_CODE (XEXP (e1, 1)) != CONST_INT)
+ if (!REG_P (XEXP (e1, 0))
+ || !CONST_INT_P (XEXP (e1, 1)))
abort ();
reg = REGNO (XEXP (e1, 0));
offset = INTVAL (XEXP (e1, 1));
HARD_FRAME_POINTER_REGNUM, reg,
offset);
}
- else if (GET_CODE (e1) == REG)
+ else if (REG_P (e1))
{
reg = REGNO (e1);
asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
else
abort ();
}
- else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
+ else if (REG_P (e1) && REGNO (e1) == SP_REGNUM)
{
/* Move from sp to reg. */
asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
}
else if (GET_CODE (e1) == PLUS
- && GET_CODE (XEXP (e1, 0)) == REG
+ && REG_P (XEXP (e1, 0))
&& REGNO (XEXP (e1, 0)) == SP_REGNUM
- && GET_CODE (XEXP (e1, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (e1, 1)))
{
/* Set reg to offset from sp. */
asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
fputs ("\t.word\t", asm_out_file);
output_addr_const (asm_out_file, x);
/* Use special relocations for symbol references. */
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
fputs ("(TARGET2)", asm_out_file);
fputc ('\n', asm_out_file);
{
REAL_VALUE_TYPE r0;
- if (GET_CODE (operand) != CONST_DOUBLE)
+ if (!CONST_DOUBLE_P (operand))
return 0;
REAL_VALUE_FROM_CONST_DOUBLE (r0, operand);
bool
arm_autoinc_modes_ok_p (enum machine_mode mode, enum arm_auto_incmodes code)
{
- /* If we are soft float and we do not have ldrd
+ /* If we are soft float and we do not have ldrd
then all auto increment forms are ok. */
if (TARGET_SOFT_FLOAT && (TARGET_LDRD || GET_MODE_SIZE (mode) <= 4))
return true;
{
if (code != ARM_PRE_DEC)
return true;
- else
+ else
return false;
}
case ARM_POST_DEC:
case ARM_PRE_INC:
- /* Without LDRD and mode size greater than
+ /* Without LDRD and mode size greater than
word size, there is no point in auto-incrementing
because ldm and stm will not have these forms. */
if (!TARGET_LDRD && GET_MODE_SIZE (mode) > 4)
}
-/* Returns true if a valid comparison operation and makes
+/* Returns true if a valid comparison operation and makes
the operands in a form that is valid. */
bool
arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
if (!cmpdi_operand (*op2, mode))
*op2 = force_reg (mode, *op2);
return true;
-
+
case SFmode:
case DFmode:
if (!arm_float_compare_operand (*op1, mode))
default:
break;
}
-
+
return false;
}
"
if (TARGET_THUMB1)
{
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]);
}
"
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER"
"
- if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
+ if (TARGET_32BIT && CONST_INT_P (operands[2]))
{
arm_split_constant (PLUS, SImode, NULL_RTX,
INTVAL (operands[2]), operands[0], operands[1],
subw%?\\t%0, %1, #%n2
#"
"TARGET_32BIT
- && GET_CODE (operands[2]) == CONST_INT
+ && CONST_INT_P (operands[2])
&& !const_ok_for_op (INTVAL (operands[2]), PLUS)
&& (reload_completed || !arm_eliminable_register (operands[1]))"
[(clobber (const_int 0))]
\"#\"
};
if ((which_alternative == 2 || which_alternative == 6)
- && GET_CODE (operands[2]) == CONST_INT
+ && CONST_INT_P (operands[2])
&& INTVAL (operands[2]) < 0)
return \"sub\\t%0, %1, #%n2\";
return asms[which_alternative];
"
if (TARGET_THUMB1)
{
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]);
}
"
(match_operand:SI 2 "s_register_operand" "")))]
"TARGET_EITHER"
"
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (TARGET_32BIT)
{
sub%?\\t%0, %1, %2
sub%?\\t%0, %1, %2
#"
- "&& (GET_CODE (operands[1]) == CONST_INT
+ "&& (CONST_INT_P (operands[1])
&& !const_ok_for_arm (INTVAL (operands[1])))"
[(clobber (const_int 0))]
"
"
if (TARGET_32BIT)
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) == 255 && arm_arch6)
{
}
else /* TARGET_THUMB1 */
{
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx tmp = force_reg (SImode, operands[2]);
if (rtx_equal_p (operands[0], operands[1]))
bic%?\\t%0, %1, #%B2
#"
"TARGET_32BIT
- && GET_CODE (operands[2]) == CONST_INT
+ && CONST_INT_P (operands[2])
&& !(const_ok_for_arm (INTVAL (operands[2]))
|| const_ok_for_arm (~INTVAL (operands[2])))"
[(clobber (const_int 0))]
{
bool use_bfi = TRUE;
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
{
HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
if (use_bfi)
{
- if (GET_CODE (operands[3]) != REG)
+ if (!REG_P (operands[3]))
operands[3] = force_reg (SImode, operands[3]);
emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
else
subtarget = target;
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
{
/* Since we are inserting a known constant, we may be able to
reduce the number of bits that we have to clear so that
/* Mask out any bits in operand[3] that are not needed. */
emit_insn (gen_andsi3 (op1, operands[3], op0));
- if (GET_CODE (op0) == CONST_INT
+ if (CONST_INT_P (op0)
&& (const_ok_for_arm (mask << start_bit)
|| const_ok_for_arm (~(mask << start_bit))))
{
}
else
{
- if (GET_CODE (op0) == CONST_INT)
+ if (CONST_INT_P (op0))
{
rtx tmp = gen_reg_rtx (SImode);
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER"
"
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (TARGET_32BIT)
{
orn%?\\t%0, %1, #%B2
#"
"TARGET_32BIT
- && GET_CODE (operands[2]) == CONST_INT
+ && CONST_INT_P (operands[2])
&& !(const_ok_for_arm (INTVAL (operands[2]))
|| (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))"
[(clobber (const_int 0))]
(xor:SI (match_operand:SI 1 "s_register_operand" "")
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER"
- "if (GET_CODE (operands[2]) == CONST_INT)
+ "if (CONST_INT_P (operands[2]))
{
if (TARGET_32BIT)
{
eor%?\\t%0, %1, %2
#"
"TARGET_32BIT
- && GET_CODE (operands[2]) == CONST_INT
+ && CONST_INT_P (operands[2])
&& !const_ok_for_arm (INTVAL (operands[2]))"
[(clobber (const_int 0))]
{
(match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER"
"
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
(match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER"
"
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
operands[2] = GEN_INT (31);
"
(match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER"
"
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_32BIT"
"
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32);
else
{
"
if (TARGET_32BIT)
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
}
else /* TARGET_THUMB1 */
{
- if (GET_CODE (operands [2]) == CONST_INT)
+ if (CONST_INT_P (operands [2]))
operands [2] = force_reg (SImode, operands[2]);
}
"
rtx a = XEXP (mem, 0);
/* This can happen due to bugs in reload. */
- if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM)
+ if (REG_P (a) && REGNO (a) == SP_REGNUM)
{
rtx ops[2];
ops[0] = operands[0];
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
"TARGET_EITHER"
{
- if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM)
+ if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1]))
{
emit_insn (gen_andsi3 (operands[0],
gen_lowpart (SImode, operands[1]),
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
- "TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN"
+ "TARGET_32BIT && (!MEM_P (operands[1])) && ! BYTES_BIG_ENDIAN"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
""
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3)))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
- "TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && BYTES_BIG_ENDIAN"
+ "TARGET_32BIT && (!MEM_P (operands[1])) && BYTES_BIG_ENDIAN"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
""
rtx b = XEXP (mem, 1);
if (GET_CODE (a) == LABEL_REF
- && GET_CODE (b) == CONST_INT)
+ && CONST_INT_P (b))
return \"ldr\\t%0, %1\";
- if (GET_CODE (b) == REG)
+ if (REG_P (b))
return \"ldrsh\\t%0, %1\";
ops[1] = a;
ops[2] = const0_rtx;
}
- gcc_assert (GET_CODE (ops[1]) == REG);
+ gcc_assert (REG_P (ops[1]));
ops[0] = operands[0];
if (reg_mentioned_p (operands[2], ops[1]))
"TARGET_ARM"
"
{
- if (arm_arch4 && GET_CODE (operands[1]) == MEM)
+ if (arm_arch4 && MEM_P (operands[1]))
{
emit_insn (gen_rtx_SET (VOIDmode,
operands[0],
;;{
;; rtx insn;
;;
-;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+;; if (MEM_P (operands[0]) && MEM_P (operands[1]))
;; operands[1] = copy_to_reg (operands[1]);
-;; if (GET_CODE (operands[0]) == MEM)
+;; if (MEM_P (operands[0]))
;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]);
-;; else if (GET_CODE (operands[1]) == MEM)
+;; else if (MEM_P (operands[1]))
;; insn = gen_loadti (operands[0], XEXP (operands[1], 0));
;; else
;; FAIL;
"
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]);
}
"
if (TARGET_32BIT)
{
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]);
if (arm_general_register_operand (operands[0], SImode)
- && GET_CODE (operands[1]) == CONST_INT
+ && CONST_INT_P (operands[1])
&& !(const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1]))))
{
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]);
}
}
rtx addr = XEXP (op1, 0);
enum rtx_code code = GET_CODE (addr);
- if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT)
+ if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS)
op1 = replace_equiv_address (operands[1], force_reg (SImode, addr));
rtx addr = XEXP (op1, 0);
enum rtx_code code = GET_CODE (addr);
- if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT)
+ if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS)
op1 = replace_equiv_address (op1, force_reg (SImode, addr));
rtx op0 = operands[0];
enum rtx_code code = GET_CODE (addr);
- if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT)
+ if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS)
op0 = replace_equiv_address (op0, force_reg (SImode, addr));
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
{
if (arm_arch4)
{
emit_insn (gen_storehi_single_op (operands[0], operands[1]));
DONE;
}
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
emit_insn (gen_storeinthi (operands[0], operands[1]));
else
{
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
if (BYTES_BIG_ENDIAN)
emit_insn (gen_storehi_bigend (operands[1], operands[0]));
DONE;
}
/* Sign extend a constant, and keep it in an SImode reg. */
- else if (GET_CODE (operands[1]) == CONST_INT)
+ else if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
operands[1] = gen_lowpart (HImode, reg);
}
else if (arm_arch4 && optimize && can_create_pseudo_p ()
- && GET_CODE (operands[1]) == MEM)
+ && MEM_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
}
else if (!arm_arch4)
{
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
{
rtx base;
rtx offset = const0_rtx;
rtx reg = gen_reg_rtx (SImode);
- if ((GET_CODE (base = XEXP (operands[1], 0)) == REG
+ if ((REG_P (base = XEXP (operands[1], 0))
|| (GET_CODE (base) == PLUS
- && (GET_CODE (offset = XEXP (base, 1))
- == CONST_INT)
+ && (CONST_INT_P (offset = XEXP (base, 1)))
&& ((INTVAL(offset) & 1) != 1)
- && GET_CODE (base = XEXP (base, 0)) == REG))
+ && REG_P (base = XEXP (base, 0))))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{
rtx new_rtx;
}
}
/* Handle loading a large integer during reload. */
- else if (GET_CODE (operands[1]) == CONST_INT
+ else if (CONST_INT_P (operands[1])
&& !const_ok_for_arm (INTVAL (operands[1]))
&& !const_ok_for_arm (~INTVAL (operands[1])))
{
/* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */
- gcc_assert (GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
/* Thumb-2 can do everything except mem=mem and mem=const easily. */
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
/* Zero extend a constant, and keep it in an SImode reg. */
- else if (GET_CODE (operands[1]) == CONST_INT)
+ else if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
fixup_stack_1, by checking for other kinds of invalid addresses,
e.g. a bare reference to a virtual register. This may confuse the
alpha though, which must handle this case differently. */
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& !memory_address_p (GET_MODE (operands[0]),
XEXP (operands[0], 0)))
operands[0]
= replace_equiv_address (operands[0],
copy_to_reg (XEXP (operands[0], 0)));
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& !memory_address_p (GET_MODE (operands[1]),
XEXP (operands[1], 0)))
operands[1]
= replace_equiv_address (operands[1],
copy_to_reg (XEXP (operands[1], 0)));
- if (GET_CODE (operands[1]) == MEM && optimize > 0)
+ if (MEM_P (operands[1]) && optimize > 0)
{
rtx reg = gen_reg_rtx (SImode);
operands[1] = gen_lowpart (HImode, reg);
}
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
}
- else if (GET_CODE (operands[1]) == CONST_INT
+ else if (CONST_INT_P (operands[1])
&& !satisfies_constraint_I (operands[1]))
{
/* Handle loading a large integer during reload. */
/* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */
- gcc_assert (GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
/* The stack pointer can end up being taken as an index register.
Catch this case here and deal with it. */
if (GET_CODE (XEXP (operands[1], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
+ && REG_P (XEXP (XEXP (operands[1], 0), 0))
&& REGNO (XEXP (XEXP (operands[1], 0), 0)) == SP_REGNUM)
{
rtx ops[2];
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
fixup_stack_1, by checking for other kinds of invalid addresses,
e.g. a bare reference to a virtual register. This may confuse the
alpha though, which must handle this case differently. */
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& !memory_address_p (GET_MODE (operands[0]),
XEXP (operands[0], 0)))
operands[0]
= replace_equiv_address (operands[0],
copy_to_reg (XEXP (operands[0], 0)));
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& !memory_address_p (GET_MODE (operands[1]),
XEXP (operands[1], 0)))
operands[1]
copy_to_reg (XEXP (operands[1], 0)));
}
- if (GET_CODE (operands[1]) == MEM && optimize > 0)
+ if (MEM_P (operands[1]) && optimize > 0)
{
rtx reg = gen_reg_rtx (SImode);
operands[1] = gen_lowpart (QImode, reg);
}
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]);
}
else if (TARGET_THUMB
- && GET_CODE (operands[1]) == CONST_INT
+ && CONST_INT_P (operands[1])
&& !satisfies_constraint_I (operands[1]))
{
/* Handle loading a large integer during reload. */
/* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */
- gcc_assert (GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
"
if (TARGET_32BIT)
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (HFmode, operands[1]);
}
else /* TARGET_THUMB1 */
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (HFmode, operands[1]);
}
}
case 1:
{
rtx addr;
- gcc_assert (GET_CODE(operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
addr = XEXP (operands[1], 0);
if (GET_CODE (addr) == LABEL_REF
|| (GET_CODE (addr) == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT))
+ && CONST_INT_P (XEXP (XEXP (addr, 0), 1))))
{
/* Constant pool entry. */
return \"ldr\\t%0, %1\";
"
if (TARGET_32BIT)
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]);
}
else /* TARGET_THUMB1 */
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]);
}
}
(match_operand:SF 1 "immediate_operand" ""))]
"TARGET_EITHER
&& reload_completed
- && GET_CODE (operands[1]) == CONST_DOUBLE"
+ && CONST_DOUBLE_P (operands[1])"
[(set (match_dup 2) (match_dup 3))]
"
operands[2] = gen_lowpart (SImode, operands[0]);
(match_operand:SF 1 "general_operand" "r,mE,r"))]
"TARGET_32BIT
&& TARGET_SOFT_FLOAT
- && (GET_CODE (operands[0]) != MEM
+ && (!MEM_P (operands[0])
|| register_operand (operands[1], SFmode))"
"@
mov%?\\t%0, %1
"
if (TARGET_32BIT)
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]);
}
else /* TARGET_THUMB */
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]);
}
}
HOST_WIDE_INT offset = 0;
/* Support only fixed point registers. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2
- || GET_CODE (operands[1]) != MEM
- || GET_CODE (operands[0]) != REG
+ || !MEM_P (operands[1])
+ || !REG_P (operands[0])
|| REGNO (operands[0]) > (LAST_ARM_REGNUM - 1)
|| REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL;
HOST_WIDE_INT offset = 0;
/* Support only fixed point registers. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2
- || GET_CODE (operands[1]) != REG
- || GET_CODE (operands[0]) != MEM
+ || !REG_P (operands[1])
+ || !MEM_P (operands[0])
|| REGNO (operands[1]) > (LAST_ARM_REGNUM - 1)
|| REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL;
gcc_assert (GET_MODE (operands[1]) == DImode
|| GET_MODE (operands[2]) == DImode);
- if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
+ if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
FAIL;
emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
operands[3]));
cond[1] = operands[2];
cond[2] = operands[3];
- if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0)
+ if (CONST_INT_P (cond[2]) && INTVAL (cond[2]) < 0)
output_asm_insn (\"sub\\t%0, %1, #%n2\", cond);
else
output_asm_insn (\"add\\t%0, %1, %2\", cond);
if (GET_CODE (operands[5]) == LT
&& (operands[4] == const0_rtx))
{
- if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
+ if (which_alternative != 1 && REG_P (operands[1]))
{
if (operands[2] == const0_rtx)
return \"and\\t%0, %1, %3, asr #31\";
return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\";
}
- else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
+ else if (which_alternative != 0 && REG_P (operands[2]))
{
if (operands[1] == const0_rtx)
return \"bic\\t%0, %2, %3, asr #31\";
if (GET_CODE (operands[5]) == GE
&& (operands[4] == const0_rtx))
{
- if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
+ if (which_alternative != 1 && REG_P (operands[1]))
{
if (operands[2] == const0_rtx)
return \"bic\\t%0, %1, %3, asr #31\";
return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\";
}
- else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
+ else if (which_alternative != 0 && REG_P (operands[2]))
{
if (operands[1] == const0_rtx)
return \"and\\t%0, %2, %3, asr #31\";
/* The only case that falls through to here is when both ops 1 & 2
are constants. */
}
- if (GET_CODE (operands[4]) == CONST_INT
+ if (CONST_INT_P (operands[4])
&& !const_ok_for_arm (INTVAL (operands[4])))
output_asm_insn (\"cmn\\t%3, #%n4\", operands);
else
everything is in registers then we can do this in two instructions. */
if (operands[3] == const0_rtx
&& GET_CODE (operands[7]) != AND
- && GET_CODE (operands[5]) == REG
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[5])
+ && REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[4])
&& REGNO (operands[4]) != REGNO (operands[0]))
{
else if (GET_CODE (operands[6]) == GE)
return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\";
}
- if (GET_CODE (operands[3]) == CONST_INT
+ if (CONST_INT_P (operands[3])
&& !const_ok_for_arm (INTVAL (operands[3])))
output_asm_insn (\"cmn\\t%2, #%n3\", operands);
else
everything is in registers then we can do this in two instructions */
if (operands[5] == const0_rtx
&& GET_CODE (operands[7]) != AND
- && GET_CODE (operands[3]) == REG
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[3])
+ && REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[2])
&& REGNO (operands[2]) != REGNO (operands[0]))
{
return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\";
}
- if (GET_CODE (operands[5]) == CONST_INT
+ if (CONST_INT_P (operands[5])
&& !const_ok_for_arm (INTVAL (operands[5])))
output_asm_insn (\"cmn\\t%4, #%n5\", operands);
else
"
{
cfun->machine->eh_epilogue_sp_ofs = operands[1];
- if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 2)
+ if (!REG_P (operands[2]) || REGNO (operands[2]) != 2)
{
rtx ra = gen_rtx_REG (Pmode, 2);