drm/xe: Clarify size of MMIO region

xe_mmio currently has a size parameter that is assigned but never used
anywhere.  The current values assigned appear to be the size of the BAR
region assigned for the tile (both for registers and other purposes such
as the GGTT).  Since the current field isn't being used for anything,
change the assignments to 4MB (the size of the register region on all
current platform) and rename the field to 'regs_size' to more clearly
describe what it represents.  We can use this value in later patches to
help ensure no register accesses accidentally go past the end of the
desired register space (which might not be caught easily if they still
fall within the iomap).

v2:
 - s/regs_length/regs_size/  (Lucas)
 - Clarify kerneldoc description (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-48-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 5d5b7a9199d8ed32ab9f2c0b9f3fff4375f8989b..ecf95801743d4f8982977da95b49393c062e4c65 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -119,8 +119,14 @@ struct xe_mmio {
        /** @regs: Map used to access registers. */
        void __iomem *regs;
 
-       /** @size: Size of the map. */
-       size_t size;
+       /**
+        * @regs_size: Length of the register region within the map.
+        *
+        * The size of the iomap set in *regs is generally larger than the
+        * register mmio space since it includes unused regions and/or
+        * non-register regions such as the GGTT PTEs.
+        */
+       size_t regs_size;
 };
 
 /**

diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 4aae30880bc61fcf6b5096e127bcb37aafdd28a1..781555bbe44960c191515c99f1aa032663d7918c 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -36,13 +36,19 @@ static void tiles_fini(void *arg)
 /*
  * On multi-tile devices, partition the BAR space for MMIO on each tile,
  * possibly accounting for register override on the number of tiles available.
+ * tile_mmio_size contains both the tile's 4MB register space, as well as
+ * additional space for the GTT and other (possibly unused) regions).
  * Resulting memory layout is like below:
  *
  * .----------------------. <- tile_count * tile_mmio_size
  * |         ....         |
  * |----------------------| <- 2 * tile_mmio_size
+ * |   tile1 GTT + other  |
+ * |----------------------| <- 1 * tile_mmio_size + 4MB
  * |   tile1->mmio.regs   |
  * |----------------------| <- 1 * tile_mmio_size
+ * |   tile0 GTT + other  |
+ * |----------------------| <- 4MB
  * |   tile0->mmio.regs   |
  * '----------------------' <- 0MB
  */
@@ -90,7 +96,7 @@ static void mmio_multi_tile_setup(struct xe_device *xe, size_t tile_mmio_size)
 
        regs = xe->mmio.regs;
        for_each_tile(tile, xe, id) {
-               tile->mmio.size = tile_mmio_size;
+               tile->mmio.regs_size = SZ_4M;
                tile->mmio.regs = regs;
                regs += tile_mmio_size;
        }
@@ -171,7 +177,7 @@ int xe_mmio_init(struct xe_device *xe)
        }
 
        /* Setup first tile; other tiles (if present) will be setup later. */
-       root_tile->mmio.size = SZ_16M;
+       root_tile->mmio.regs_size = SZ_4M;
        root_tile->mmio.regs = xe->mmio.regs;
 
        return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);