drm/i915/sbi: add intel_sbi_{lock,unlock}()

Abstract the LPT/WPT IOSF sideband locking by adding dedicated sbi
lock/unlock functions.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/61929c2fad4d4ff64e57ea2a28007f2efeb5113c.1730193891.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 84c55971e91a883b7aa3dd01c25c99307d32f3cf..d29b9adcbed15efbfd83e0ae94efa13ef1743955 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -108,13 +108,13 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
 
        intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
 
-       mutex_lock(&dev_priv->sb_lock);
+       intel_sbi_lock(dev_priv);
 
        temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
        temp |= SBI_SSCCTL_DISABLE;
        intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
 
-       mutex_unlock(&dev_priv->sb_lock);
+       intel_sbi_unlock(dev_priv);
 }
 
 struct iclkip_params {
@@ -195,7 +195,7 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
                    "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
                    clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
 
-       mutex_lock(&dev_priv->sb_lock);
+       intel_sbi_lock(dev_priv);
 
        /* Program SSCDIVINTPHASE6 */
        temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
@@ -218,7 +218,7 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
        temp &= ~SBI_SSCCTL_DISABLE;
        intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
 
-       mutex_unlock(&dev_priv->sb_lock);
+       intel_sbi_unlock(dev_priv);
 
        /* Wait for initialization time */
        udelay(24);
@@ -236,11 +236,11 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 
        iclkip_params_init(&p);
 
-       mutex_lock(&dev_priv->sb_lock);
+       intel_sbi_lock(dev_priv);
 
        temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
        if (temp & SBI_SSCCTL_DISABLE) {
-               mutex_unlock(&dev_priv->sb_lock);
+               intel_sbi_unlock(dev_priv);
                return 0;
        }
 
@@ -254,7 +254,7 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
        p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
                SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
 
-       mutex_unlock(&dev_priv->sb_lock);
+       intel_sbi_unlock(dev_priv);
 
        p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc;
 
@@ -279,7 +279,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
                     with_fdi, "LP PCH doesn't have FDI\n"))
                with_fdi = false;
 
-       mutex_lock(&dev_priv->sb_lock);
+       intel_sbi_lock(dev_priv);
 
        tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
        tmp &= ~SBI_SSCCTL_DISABLE;
@@ -302,7 +302,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
        tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
        intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
 
-       mutex_unlock(&dev_priv->sb_lock);
+       intel_sbi_unlock(dev_priv);
 }
 
 /* Sequence to disable CLKOUT_DP */
@@ -310,7 +310,7 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
 {
        u32 reg, tmp;
 
-       mutex_lock(&dev_priv->sb_lock);
+       intel_sbi_lock(dev_priv);
 
        reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
        tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
@@ -328,7 +328,7 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
                intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
        }
 
-       mutex_unlock(&dev_priv->sb_lock);
+       intel_sbi_unlock(dev_priv);
 }
 
 #define BEND_IDX(steps) ((50 + (steps)) / 5)
@@ -374,7 +374,7 @@ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
        if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
                return;
 
-       mutex_lock(&dev_priv->sb_lock);
+       intel_sbi_lock(dev_priv);
 
        if (steps % 10 != 0)
                tmp = 0xAAAAAAAB;
@@ -387,7 +387,7 @@ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
        tmp |= sscdivintphase[idx];
        intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
 
-       mutex_unlock(&dev_priv->sb_lock);
+       intel_sbi_unlock(dev_priv);
 }
 
 #undef BEND_IDX

diff --git a/drivers/gpu/drm/i915/intel_sbi.c b/drivers/gpu/drm/i915/intel_sbi.c
index 5c6e517c73f499d706e734d23751b1846aaaab9d..862b5b9992eb8ad745116ae6c385279d008bdd47 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sbi.c
+++ b/drivers/gpu/drm/i915/intel_sbi.c
@@ -57,6 +57,16 @@ static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
        return 0;
 }
 
+void intel_sbi_lock(struct drm_i915_private *i915)
+{
+       mutex_lock(&i915->sb_lock);
+}
+
+void intel_sbi_unlock(struct drm_i915_private *i915)
+{
+       mutex_unlock(&i915->sb_lock);
+}
+
 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
                   enum intel_sbi_destination destination)
 {

diff --git a/drivers/gpu/drm/i915/intel_sbi.h b/drivers/gpu/drm/i915/intel_sbi.h
index f5a862210454ba251bfb9ee98d9d950f1143830c..f91bd03aa82643b39ebb963226a0c2f1a5b1d38b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sbi.h
+++ b/drivers/gpu/drm/i915/intel_sbi.h
@@ -15,6 +15,8 @@ enum intel_sbi_destination {
        SBI_MPHY,
 };
 
+void intel_sbi_lock(struct drm_i915_private *i915);
+void intel_sbi_unlock(struct drm_i915_private *i915);
 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
                   enum intel_sbi_destination destination);
 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,