RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine

The vwaddu and vwsubu combine pattern should take plus/minus
instead of any_widen_binop.  This PATCH would like to fix it.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Take concrete op instead
	of any_widen_binop for vwaddu/vwsubu wx combine.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 3d6e0a19c8a5e92c472afa735620ace2565da636..d2705cf0fb92b405f9cd0034b1828587bbe089e7 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1913,7 +1913,7 @@
 
 (define_insn_and_split "*widen_waddu_wx_<mode>"
  [(set (match_operand:VWEXTI_D       0 "register_operand")
-       (any_widen_binop:VWEXTI_D
+       (plus:VWEXTI_D
         (vec_duplicate:VWEXTI_D
           (any_extend:<VEL>
             (match_operand:<VSUBEL> 2 "register_operand")))
@@ -1933,7 +1933,7 @@
 
 (define_insn_and_split "*widen_wsubu_wx_<mode>"
  [(set (match_operand:VWEXTI_D       0 "register_operand")
-       (any_widen_binop:VWEXTI_D
+       (minus:VWEXTI_D
         (match_operand:VWEXTI_D     1 "register_operand")
         (vec_duplicate:VWEXTI_D
           (any_extend:<VEL>