arm64: dts: imx8qxp-mek: change space with tab

Change space with tab to align with code style.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 2e174ac35d4b5050600820f1d7634f97a22827a5..523f48896b6b8e57c4c8eeaeb13716225d16dde6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -874,8 +874,8 @@
 
        pinctrl_cm40_i2c: cm40i2cgrp {
                fsl,pins = <
-                       IMX8QXP_ADC_IN1_M40_I2C0_SDA                            0x0600004c
-                       IMX8QXP_ADC_IN0_M40_I2C0_SCL                            0x0600004c
+                       IMX8QXP_ADC_IN1_M40_I2C0_SDA                            0x0600004c
+                       IMX8QXP_ADC_IN0_M40_I2C0_SCL                            0x0600004c
                >;
        };
 
@@ -888,16 +888,16 @@
 
        pinctrl_esai0: esai0grp {
                fsl,pins = <
-                       IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR           0xc6000040
-                       IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST           0xc6000040
-                       IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR         0xc6000040
-                       IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT         0xc6000040
-                       IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0           0xc6000040
-                       IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1           0xc6000040
-                       IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3   0xc6000040
-                       IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2   0xc6000040
-                       IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1   0xc6000040
-                       IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0   0xc6000040
+                       IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR                        0xc6000040
+                       IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST                        0xc6000040
+                       IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR                      0xc6000040
+                       IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT                      0xc6000040
+                       IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0                        0xc6000040
+                       IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1                        0xc6000040
+                       IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3                0xc6000040
+                       IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2                0xc6000040
+                       IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1                0xc6000040
+                       IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0                0xc6000040
                >;
        };
 
@@ -1016,15 +1016,15 @@
 
        pinctrl_lpuart2: lpuart2grp {
                fsl,pins = <
-                       IMX8QXP_UART2_TX_ADMA_UART2_TX          0x06000020
-                       IMX8QXP_UART2_RX_ADMA_UART2_RX          0x06000020
+                       IMX8QXP_UART2_TX_ADMA_UART2_TX                          0x06000020
+                       IMX8QXP_UART2_RX_ADMA_UART2_RX                          0x06000020
                >;
        };
 
        pinctrl_lpuart3: lpuart3grp {
                fsl,pins = <
-                       IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX       0x06000020
-                       IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX       0x06000020
+                       IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX                       0x06000020
+                       IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX                       0x06000020
                >;
        };
 
@@ -1046,13 +1046,13 @@
 
        pinctrl_typec: typecgrp {
                fsl,pins = <
-                       IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03                        0x06000021
+                       IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03                        0x06000021
                >;
        };
 
        pinctrl_typec_mux: typecmuxgrp {
                fsl,pins = <
-                       IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09           0x60
+                       IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09           0x60
                >;
        };
 
@@ -1067,11 +1067,11 @@
 
        pinctrl_sai1: sai1grp {
                fsl,pins = <
-                       IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD     0x06000040
-                       IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC     0x06000040
-                       IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS   0x06000040
-                       IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD     0x06000060
-                       IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00   0x06000040
+                       IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD                          0x06000040
+                       IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC                          0x06000040
+                       IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS                        0x06000040
+                       IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD                          0x06000060
+                       IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00                        0x06000040
                >;
        };