target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH

Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by
Coverity (CID 1395627).

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2890219f0b0472764a15c494aedfbaebbb4ae5cd..12f2aecf7e5828e74bfddefea121873677dbbd41 100644 (file)
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19970,8 +19970,8 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
         case 0:
             /* SHRA_PH */
             gen_helper_shra_ph(v1_t, t0, v1_t);
-            break;
             gen_store_gpr(v1_t, rt);
+            break;
         case 1:
             /* SHRA_R_PH */
             gen_helper_shra_r_ph(v1_t, t0, v1_t);