drm/msm/adreno: Add support for X185 GPU

Add support in drm/msm driver for the Adreno X185 gpu found in
Snapdragon X1 Elite chipset.

Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/601399/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 53e33ff784118d82e1682e5c42d1cb5b12ef6112..c507681648ac98029276b77d0f93e6572392f5b3 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1208,6 +1208,24 @@ static const struct adreno_info a7xx_gpus[] = {
                        .protect = &a730_protect,
                },
                .address_space_size = SZ_16G,
+       }, {
+               .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
+               .family = ADRENO_7XX_GEN2,
+               .fw = {
+                       [ADRENO_FW_SQE] = "gen70500_sqe.fw",
+                       [ADRENO_FW_GMU] = "gen70500_gmu.bin",
+               },
+               .gmem = 3 * SZ_1M,
+               .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_HAS_HW_APRIV,
+               .init = a6xx_gpu_init,
+               .a6xx = &(const struct a6xx_info) {
+                       .hwcg = a740_hwcg,
+                       .protect = &a730_protect,
+                       .gmu_chipid = 0x7050001,
+               },
+               .address_space_size = SZ_256G,
        }, {
                .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
                .family = ADRENO_7XX_GEN3,

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 09d640165b1881a62aa13035f9d4cb3b488364a2..400e5cbe4b35b2759a526ceb4908f3039c0e6e68 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -767,6 +767,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
 {
        struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx;
        u32 fence_range_lower, fence_range_upper;
        u32 chipid, chipid_min = 0;
        int ret;
@@ -828,8 +829,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
         */
        gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
 
+       if (a6xx_info->gmu_chipid) {
+               chipid = a6xx_info->gmu_chipid;
        /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */
-       if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) {
+       } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) {
                /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */
                chipid = FIELD_PREP(GENMASK(31, 24), 0x7);
 
@@ -1327,7 +1330,13 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
        if (!pri_count)
                return -EINVAL;
 
-       sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
+       /*
+        * Some targets have a separate gfx mxc rail. So try to read that first and then fall back
+        * to regular mx rail if it is missing
+        */
+       sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count);
+       if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER))
+               sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
        if (IS_ERR(sec))
                return PTR_ERR(sec);
 

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 95c7024ef247a72703aa4f7dcfd26a97c1592590..bcaec86ac67a5c90544922372cd46fbdd8cf359e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1029,7 +1029,7 @@ static int hw_init(struct msm_gpu *gpu)
        gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1);
 
        /* Set weights for bicubic filtering */
-       if (adreno_is_a650_family(adreno_gpu)) {
+       if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) {
                gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
                gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
                        0x3fe05ff4);

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 1c3cc6df70fe2e0577d36146ce4acee118c22b28..e3e5c53ae8af2cc59a21160f05c59fd125cb94b1 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -21,6 +21,7 @@ extern bool hang_debug;
 struct a6xx_info {
        const struct adreno_reglist *hwcg;
        const struct adreno_protect *protect;
+       u32 gmu_chipid;
 };
 
 struct a6xx_gpu {

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index cff8ce541d2c3568fc804a8af46a78e66367111a..e1c69bb022d6550a437773bffe2cc6619553badb 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -474,6 +474,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu)
        return gpu->info->chip_ids[0] == 0x43051401;
 }
 
+static inline int adreno_is_x185(struct adreno_gpu *gpu)
+{
+       return gpu->info->chip_ids[0] == 0x43050c01;
+}
+
 static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
 {
        if (WARN_ON_ONCE(!gpu->info))