3.10-stable patches

added patches:
	drm-i915-use-the-correct-gmch_ctrl-register-for-sandybridge.patch
	drm-radeon-fix-asic-gfx-values-for-scrapper-asics.patch

diff --git a/queue-3.10/drm-i915-use-the-correct-gmch_ctrl-register-for-sandybridge.patch b/queue-3.10/drm-i915-use-the-correct-gmch_ctrl-register-for-sandybridge.patch
new file mode 100644 (file)
index 0000000..8f9f6be
--- /dev/null
+++ b/queue-3.10/drm-i915-use-the-correct-gmch_ctrl-register-for-sandybridge.patch
@@ -0,0 +1,48 @@
+From a885b3ccc74d8e38074e1c43a47c354c5ea0b01e Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Tue, 17 Dec 2013 14:34:50 +0000
+Subject: drm/i915: Use the correct GMCH_CTRL register for Sandybridge+
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit a885b3ccc74d8e38074e1c43a47c354c5ea0b01e upstream.
+
+The GMCH_CTRL register (or MGCC in the spec) is at a different address
+on Sandybridge, and the address to which we currently write to is
+undefined. These stray writes appear to upset (hard hang) my Ivybridge
+machine whilst it is in UEFI mode.
+
+Note that the register is still marked as locked RO on Sandybridge, so
+vgaarb is still dysfunctional.
+
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_display.c |    5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -9532,14 +9532,15 @@ void intel_connector_attach_encoder(stru
+ int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
+ {
+       struct drm_i915_private *dev_priv = dev->dev_private;
++      unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
+       u16 gmch_ctrl;
+ 
+-      pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
++      pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
+       if (state)
+               gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
+       else
+               gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
+-      pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
++      pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
+       return 0;
+ }
+ 

diff --git a/queue-3.10/drm-radeon-fix-asic-gfx-values-for-scrapper-asics.patch b/queue-3.10/drm-radeon-fix-asic-gfx-values-for-scrapper-asics.patch
new file mode 100644 (file)
index 0000000..3495328
--- /dev/null
+++ b/queue-3.10/drm-radeon-fix-asic-gfx-values-for-scrapper-asics.patch
@@ -0,0 +1,74 @@
+From e2f6c88fb903e123edfd1106b0b8310d5117f774 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Dec 2013 19:41:46 -0500
+Subject: drm/radeon: fix asic gfx values for scrapper asics
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit e2f6c88fb903e123edfd1106b0b8310d5117f774 upstream.
+
+Fixes gfx corruption on certain TN/RL parts.
+
+bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=60389
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/ni.c |   20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -753,6 +753,10 @@ static void cayman_gpu_init(struct radeo
+                   (rdev->pdev->device == 0x999C)) {
+                       rdev->config.cayman.max_simds_per_se = 6;
+                       rdev->config.cayman.max_backends_per_se = 2;
++                      rdev->config.cayman.max_hw_contexts = 8;
++                      rdev->config.cayman.sx_max_export_size = 256;
++                      rdev->config.cayman.sx_max_export_pos_size = 64;
++                      rdev->config.cayman.sx_max_export_smx_size = 192;
+               } else if ((rdev->pdev->device == 0x9903) ||
+                          (rdev->pdev->device == 0x9904) ||
+                          (rdev->pdev->device == 0x990A) ||
+@@ -763,6 +767,10 @@ static void cayman_gpu_init(struct radeo
+                          (rdev->pdev->device == 0x999D)) {
+                       rdev->config.cayman.max_simds_per_se = 4;
+                       rdev->config.cayman.max_backends_per_se = 2;
++                      rdev->config.cayman.max_hw_contexts = 8;
++                      rdev->config.cayman.sx_max_export_size = 256;
++                      rdev->config.cayman.sx_max_export_pos_size = 64;
++                      rdev->config.cayman.sx_max_export_smx_size = 192;
+               } else if ((rdev->pdev->device == 0x9919) ||
+                          (rdev->pdev->device == 0x9990) ||
+                          (rdev->pdev->device == 0x9991) ||
+@@ -773,9 +781,17 @@ static void cayman_gpu_init(struct radeo
+                          (rdev->pdev->device == 0x99A0)) {
+                       rdev->config.cayman.max_simds_per_se = 3;
+                       rdev->config.cayman.max_backends_per_se = 1;
++                      rdev->config.cayman.max_hw_contexts = 4;
++                      rdev->config.cayman.sx_max_export_size = 128;
++                      rdev->config.cayman.sx_max_export_pos_size = 32;
++                      rdev->config.cayman.sx_max_export_smx_size = 96;
+               } else {
+                       rdev->config.cayman.max_simds_per_se = 2;
+                       rdev->config.cayman.max_backends_per_se = 1;
++                      rdev->config.cayman.max_hw_contexts = 4;
++                      rdev->config.cayman.sx_max_export_size = 128;
++                      rdev->config.cayman.sx_max_export_pos_size = 32;
++                      rdev->config.cayman.sx_max_export_smx_size = 96;
+               }
+               rdev->config.cayman.max_texture_channel_caches = 2;
+               rdev->config.cayman.max_gprs = 256;
+@@ -783,10 +799,6 @@ static void cayman_gpu_init(struct radeo
+               rdev->config.cayman.max_gs_threads = 32;
+               rdev->config.cayman.max_stack_entries = 512;
+               rdev->config.cayman.sx_num_of_sets = 8;
+-              rdev->config.cayman.sx_max_export_size = 256;
+-              rdev->config.cayman.sx_max_export_pos_size = 64;
+-              rdev->config.cayman.sx_max_export_smx_size = 192;
+-              rdev->config.cayman.max_hw_contexts = 8;
+               rdev->config.cayman.sq_num_cf_insts = 2;
+ 
+               rdev->config.cayman.sc_prim_fifo_size = 0x40;

diff --git a/queue-3.10/series b/queue-3.10/series
index f28b5eab4062a3189b1d179514a2977d876f4ec0..56e7508353f48165e9ccd216ea2ec2ce94c7472e 100644 (file)
--- a/queue-3.10/series
+++ b/queue-3.10/series
@@ -43,3 +43,5 @@ drm-radeon-add-missing-display-tiling-setup-for-oland.patch
 drm-i915-take-modeset-locks-around-intel_modeset_setup_hw_state.patch
 drm-i915-hold-mutex-across-i915_gem_release.patch
 drm-i915-don-t-update-the-dri1-breadcrumb-with-modesetting.patch
+drm-radeon-fix-asic-gfx-values-for-scrapper-asics.patch
+drm-i915-use-the-correct-gmch_ctrl-register-for-sandybridge.patch