--- /dev/null
+From 64d91cfaade2155ad048fe3b65238a052e29dde4 Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
+Date: Fri, 7 Oct 2011 13:39:49 +0900
+Subject: 8250_pci: Fix kernel panic when pch_uart is disabled
+
+From: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
+
+commit 64d91cfaade2155ad048fe3b65238a052e29dde4 upstream.
+
+Currently, ".setup" function is not set.
+As a result, when detecting our IOH's uart device without pch_uart, kernel panic
+occurs at the following of pciserial_init_ports().
+
+ for (i = 0; i < nr_ports; i++) {
+ if (quirk->setup(priv, board, &serial_port, i))
+ break;
+
+So, this patch adds the ".setup" function.
+We can use pci_default_setup because our IOH's uart is compatible with 16550.
+
+Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
+Acked-by: Alan Cox <alan@linux.intel.com>
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/tty/serial/8250_pci.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/tty/serial/8250_pci.c
++++ b/drivers/tty/serial/8250_pci.c
+@@ -1459,51 +1459,61 @@ static struct pci_serial_quirk pci_seria
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x8811,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x8812,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x8813,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x8814,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = 0x10DB,
+ .device = 0x8027,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = 0x10DB,
+ .device = 0x8028,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = 0x10DB,
+ .device = 0x8029,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = 0x10DB,
+ .device = 0x800C,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = 0x10DB,
+ .device = 0x800D,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ {
+ .vendor = 0x10DB,
+ .device = 0x800D,
+ .init = pci_eg20t_init,
++ .setup = pci_default_setup,
+ },
+ /*
+ * Cronyx Omega PCI (PLX-chip based)
--- /dev/null
+From 70f18915846f092e0e1c988f1726a532fa3ab3a1 Mon Sep 17 00:00:00 2001
+From: Alexander Stein <alexander.stein@systec-electronic.com>
+Date: Wed, 22 Jun 2011 17:05:33 +0200
+Subject: pch_dma: Fix channel locking
+
+From: Alexander Stein <alexander.stein@systec-electronic.com>
+
+commit 70f18915846f092e0e1c988f1726a532fa3ab3a1 upstream.
+
+Fix for the following INFO message
+
+=================================
+[ INFO: inconsistent lock state ]
+2.6.39+ #89
+---------------------------------
+inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usage.
+rs232/822 [HC1[1]:SC0[0]:HE0:SE1] takes:
+ (&(&pd_chan->lock)->rlock){?.....}, at: [<c123b9a1>] pdc_desc_get+0x16/0xab
+{HARDIRQ-ON-W} state was registered at:
+ [<c104fe28>] mark_irqflags+0xbd/0x11a
+ [<c1050386>] __lock_acquire+0x501/0x6bb
+ [<c1050945>] lock_acquire+0x63/0x7b
+ [<c131c51d>] _raw_spin_lock_bh+0x43/0x51
+ [<c123bee4>] pd_alloc_chan_resources+0x92/0x11e
+ [<c123ad62>] dma_chan_get+0x9b/0x107
+ [<c123b2d1>] __dma_request_channel+0x61/0xdc
+ [<c11ba24b>] pch_request_dma+0x61/0x19e
+ [<c11bb3b8>] pch_uart_startup+0x16a/0x1a2
+ [<c11b8446>] uart_startup+0x87/0x147
+ [<c11b9183>] uart_open+0x117/0x13e
+ [<c11a5c7d>] tty_open+0x23c/0x34c
+ [<c1097705>] chrdev_open+0x140/0x15f
+ [<c10930a6>] __dentry_open.clone.14+0x14a/0x22b
+ [<c1093dfb>] nameidata_to_filp+0x36/0x40
+ [<c109f28b>] do_last+0x513/0x635
+ [<c109f4af>] path_openat+0x9c/0x2aa
+ [<c109f6e4>] do_filp_open+0x27/0x69
+ [<c1093f02>] do_sys_open+0xfd/0x184
+ [<c1093fad>] sys_open+0x24/0x2a
+ [<c131d58c>] sysenter_do_call+0x12/0x32
+irq event stamp: 2522
+hardirqs last enabled at (2521): [<c131ca3b>] _raw_spin_unlock_irqrestore+0x36/0x52
+hardirqs last disabled at (2522): [<c131db27>] common_interrupt+0x27/0x34
+softirqs last enabled at (2354): [<c102fa11>] __do_softirq+0x10a/0x11a
+softirqs last disabled at (2299): [<c10041a4>] do_softirq+0x57/0xa4
+
+other info that might help us debug this:
+2 locks held by rs232/822:
+ #0: (&tty->atomic_write_lock){+.+.+.}, at: [<c11a4b7a>] tty_write_lock+0x14/0x3c
+ #1: (&port_lock_key){-.....}, at: [<c11bad72>] pch_uart_interrupt+0x17/0x1e9
+
+stack backtrace:
+Pid: 822, comm: rs232 Not tainted 2.6.39+ #89
+Call Trace:
+ [<c1319f90>] ? printk+0x19/0x1b
+ [<c104f893>] print_usage_bug+0x184/0x18f
+ [<c104e5b1>] ? print_irq_inversion_bug+0x10e/0x10e
+ [<c104f943>] mark_lock_irq+0xa5/0x1f6
+ [<c104fc9c>] mark_lock+0x208/0x2d7
+ [<c104fdc0>] mark_irqflags+0x55/0x11a
+ [<c1050386>] __lock_acquire+0x501/0x6bb
+ [<c10042ee>] ? dump_trace+0x92/0xb6
+ [<c1050945>] lock_acquire+0x63/0x7b
+ [<c123b9a1>] ? pdc_desc_get+0x16/0xab
+ [<c131c2d0>] _raw_spin_lock+0x3e/0x4c
+ [<c123b9a1>] ? pdc_desc_get+0x16/0xab
+ [<c123b9a1>] pdc_desc_get+0x16/0xab
+ [<c10504d8>] ? __lock_acquire+0x653/0x6bb
+ [<c123bb2c>] pd_prep_slave_sg+0x7c/0x1cb
+ [<c1006c3f>] ? nommu_map_sg+0x6e/0x81
+ [<c11bace6>] dma_handle_tx+0x2cf/0x344
+ [<c11bad72>] ? pch_uart_interrupt+0x17/0x1e9
+ [<c11baebb>] pch_uart_interrupt+0x160/0x1e9
+ [<c10642fb>] handle_irq_event_percpu+0x25/0x127
+ [<c1064429>] handle_irq_event+0x2c/0x43
+ [<c1065e0d>] ? handle_fasteoi_irq+0x84/0x84
+ [<c1065eb9>] handle_edge_irq+0xac/0xce
+ <IRQ> [<c1003ecb>] ? do_IRQ+0x38/0x9d
+ [<c131db2e>] ? common_interrupt+0x2e/0x34
+ [<c105007b>] ? __lock_acquire+0x1f6/0x6bb
+ [<c131ca3d>] ? _raw_spin_unlock_irqrestore+0x38/0x52
+ [<c11b798b>] ? uart_start+0x2d/0x32
+ [<c11b7998>] ? uart_flush_chars+0x8/0xa
+ [<c11a7962>] ? n_tty_write+0x12c/0x1c6
+ [<c1027a73>] ? try_to_wake_up+0x251/0x251
+ [<c11a4d0b>] ? tty_write+0x169/0x1dc
+ [<c11a7836>] ? n_tty_ioctl+0xb7/0xb7
+ [<c1094841>] ? vfs_write+0x91/0x10d
+ [<c11a4ba2>] ? tty_write_lock+0x3c/0x3c
+ [<c1094a69>] ? sys_write+0x3e/0x63
+ [<c131d58c>] ? sysenter_do_call+0x12/0x32
+
+Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
+Tested-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/dma/pch_dma.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/dma/pch_dma.c
++++ b/drivers/dma/pch_dma.c
+@@ -521,11 +521,11 @@ static int pd_alloc_chan_resources(struc
+ list_add_tail(&desc->desc_node, &tmp_list);
+ }
+
+- spin_lock_bh(&pd_chan->lock);
++ spin_lock_irq(&pd_chan->lock);
+ list_splice(&tmp_list, &pd_chan->free_list);
+ pd_chan->descs_allocated = i;
+ pd_chan->completed_cookie = chan->cookie = 1;
+- spin_unlock_bh(&pd_chan->lock);
++ spin_unlock_irq(&pd_chan->lock);
+
+ pdc_enable_irq(chan, 1);
+
+@@ -543,10 +543,10 @@ static void pd_free_chan_resources(struc
+ BUG_ON(!list_empty(&pd_chan->active_list));
+ BUG_ON(!list_empty(&pd_chan->queue));
+
+- spin_lock_bh(&pd_chan->lock);
++ spin_lock_irq(&pd_chan->lock);
+ list_splice_init(&pd_chan->free_list, &tmp_list);
+ pd_chan->descs_allocated = 0;
+- spin_unlock_bh(&pd_chan->lock);
++ spin_unlock_irq(&pd_chan->lock);
+
+ list_for_each_entry_safe(desc, _d, &tmp_list, desc_node)
+ pci_pool_free(pd->pool, desc, desc->txd.phys);
+@@ -562,10 +562,10 @@ static enum dma_status pd_tx_status(stru
+ dma_cookie_t last_completed;
+ int ret;
+
+- spin_lock_bh(&pd_chan->lock);
++ spin_lock_irq(&pd_chan->lock);
+ last_completed = pd_chan->completed_cookie;
+ last_used = chan->cookie;
+- spin_unlock_bh(&pd_chan->lock);
++ spin_unlock_irq(&pd_chan->lock);
+
+ ret = dma_async_is_complete(cookie, last_completed, last_used);
+
+@@ -680,7 +680,7 @@ static int pd_device_control(struct dma_
+ if (cmd != DMA_TERMINATE_ALL)
+ return -ENXIO;
+
+- spin_lock_bh(&pd_chan->lock);
++ spin_lock_irq(&pd_chan->lock);
+
+ pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE);
+
+@@ -690,7 +690,7 @@ static int pd_device_control(struct dma_
+ list_for_each_entry_safe(desc, _d, &list, desc_node)
+ pdc_chain_complete(pd_chan, desc);
+
+- spin_unlock_bh(&pd_chan->lock);
++ spin_unlock_irq(&pd_chan->lock);
+
+ return 0;
+ }
--- /dev/null
+From 0b052f4a088ddc47a5da23dd733522241314cfb4 Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+Date: Thu, 14 Jul 2011 09:52:38 +0900
+Subject: pch_dma: Fix CTL register access issue
+
+From: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+
+commit 0b052f4a088ddc47a5da23dd733522241314cfb4 upstream.
+
+Currently, Mode-Control register is accessed by read-modify-write.
+
+According to DMA hardware specifications datasheet, prohibits this method.
+Because this register resets to 0 by DMA HW after DMA transfer completes.
+Thus, current read-modify-write processing can cause unexpected behavior.
+
+The datasheet says in case of writing Mode-Control register, set the value for only target channel, the others must set '11b'.
+e.g. Set DMA0=01b DMA11=10b
+CTL0=33333331h
+CTL2=00002333h
+
+NOTE:
+CTL0 includes DMA0~7 Mode-Control register.
+CTL2 includes DMA8~11 Mode-Control register.
+
+This patch modifies the issue.
+
+Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/dma/pch_dma.c | 42 +++++++++++++++++++++++++++++++-----------
+ 1 file changed, 31 insertions(+), 11 deletions(-)
+
+--- a/drivers/dma/pch_dma.c
++++ b/drivers/dma/pch_dma.c
+@@ -62,6 +62,9 @@
+
+ #define MAX_CHAN_NR 8
+
++#define DMA_MASK_CTL0_MODE 0x33333333
++#define DMA_MASK_CTL2_MODE 0x00003333
++
+ static unsigned int init_nr_desc_per_channel = 64;
+ module_param(init_nr_desc_per_channel, uint, 0644);
+ MODULE_PARM_DESC(init_nr_desc_per_channel,
+@@ -210,10 +213,17 @@ static void pdc_set_dir(struct dma_chan
+ struct pch_dma_chan *pd_chan = to_pd_chan(chan);
+ struct pch_dma *pd = to_pd(chan->device);
+ u32 val;
++ u32 mask_mode;
++ u32 mask_ctl;
+
+ if (chan->chan_id < 8) {
+ val = dma_readl(pd, CTL0);
+
++ mask_mode = DMA_CTL0_MODE_MASK_BITS <<
++ (DMA_CTL0_BITS_PER_CH * chan->chan_id);
++ mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
++ (DMA_CTL0_BITS_PER_CH * chan->chan_id));
++ val &= mask_mode;
+ if (pd_chan->dir == DMA_TO_DEVICE)
+ val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
+ DMA_CTL0_DIR_SHIFT_BITS);
+@@ -221,18 +231,24 @@ static void pdc_set_dir(struct dma_chan
+ val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
+ DMA_CTL0_DIR_SHIFT_BITS));
+
++ val |= mask_ctl;
+ dma_writel(pd, CTL0, val);
+ } else {
+ int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
+ val = dma_readl(pd, CTL3);
+
++ mask_mode = DMA_CTL0_MODE_MASK_BITS <<
++ (DMA_CTL0_BITS_PER_CH * ch);
++ mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
++ (DMA_CTL0_BITS_PER_CH * ch));
++ val &= mask_mode;
+ if (pd_chan->dir == DMA_TO_DEVICE)
+ val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
+ DMA_CTL0_DIR_SHIFT_BITS);
+ else
+ val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch +
+ DMA_CTL0_DIR_SHIFT_BITS));
+-
++ val |= mask_ctl;
+ dma_writel(pd, CTL3, val);
+ }
+
+@@ -244,26 +260,30 @@ static void pdc_set_mode(struct dma_chan
+ {
+ struct pch_dma *pd = to_pd(chan->device);
+ u32 val;
++ u32 mask_ctl;
++ u32 mask_dir;
+
+ if (chan->chan_id < 8) {
++ mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
++ (DMA_CTL0_BITS_PER_CH * chan->chan_id));
++ mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +\
++ DMA_CTL0_DIR_SHIFT_BITS);
+ val = dma_readl(pd, CTL0);
+-
+- val &= ~(DMA_CTL0_MODE_MASK_BITS <<
+- (DMA_CTL0_BITS_PER_CH * chan->chan_id));
++ val &= mask_dir;
+ val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
+-
++ val |= mask_ctl;
+ dma_writel(pd, CTL0, val);
+ } else {
+ int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
+-
++ mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
++ (DMA_CTL0_BITS_PER_CH * ch));
++ mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * ch +\
++ DMA_CTL0_DIR_SHIFT_BITS);
+ val = dma_readl(pd, CTL3);
+-
+- val &= ~(DMA_CTL0_MODE_MASK_BITS <<
+- (DMA_CTL0_BITS_PER_CH * ch));
++ val &= mask_dir;
+ val |= mode << (DMA_CTL0_BITS_PER_CH * ch);
+-
++ val |= mask_ctl;
+ dma_writel(pd, CTL3, val);
+-
+ }
+
+ dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
--- /dev/null
+From c3d4913cd4cd469cbf29d411293e937729e83f3a Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+Date: Tue, 31 May 2011 10:34:45 +0900
+Subject: pch_dma: fix DMA issue(ch8-ch11)
+
+From: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+
+commit c3d4913cd4cd469cbf29d411293e937729e83f3a upstream.
+
+ISSUE: In case PCH_DMA with I2S communications with ch8~ch11, sometimes I2S data
+is not send correctly.
+CAUSE: The following patch I submitted before was not enough modification for
+supporting DMA ch8~ch11. The modification for status register of ch8~11 was not
+enough.
+
+pch_dma: Support I2S for ML7213 IOH
+author Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+ Mon, 9 May 2011 07:09:38 +0000 (16:09 +0900)
+committer Vinod Koul <vinod.koul@intel.com>
+ Mon, 9 May 2011 11:42:23 +0000 (16:42 +0530)
+commit 194f5f2706c7472f9c6bb2d17fa788993606581f
+tree c9d4903ea02b18939a4f390956a48be1a3734517
+parent 60092d0bde4c8741198da4a69b693d3709385bf1
+
+This patch fixes the issue.
+We can confirm PCH_DMA with I2S communications with ch8~ch11 works well.
+
+Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/dma/pch_dma.c | 71 +++++++++++++++++++++++++++++++++++++++-----------
+ 1 file changed, 56 insertions(+), 15 deletions(-)
+
+--- a/drivers/dma/pch_dma.c
++++ b/drivers/dma/pch_dma.c
+@@ -45,7 +45,8 @@
+ #define DMA_STATUS_MASK_BITS 0x3
+ #define DMA_STATUS_SHIFT_BITS 16
+ #define DMA_STATUS_IRQ(x) (0x1 << (x))
+-#define DMA_STATUS_ERR(x) (0x1 << ((x) + 8))
++#define DMA_STATUS0_ERR(x) (0x1 << ((x) + 8))
++#define DMA_STATUS2_ERR(x) (0x1 << (x))
+
+ #define DMA_DESC_WIDTH_SHIFT_BITS 12
+ #define DMA_DESC_WIDTH_1_BYTE (0x3 << DMA_DESC_WIDTH_SHIFT_BITS)
+@@ -133,6 +134,7 @@ struct pch_dma {
+ #define PCH_DMA_CTL3 0x0C
+ #define PCH_DMA_STS0 0x10
+ #define PCH_DMA_STS1 0x14
++#define PCH_DMA_STS2 0x18
+
+ #define dma_readl(pd, name) \
+ readl((pd)->membase + PCH_DMA_##name)
+@@ -183,13 +185,19 @@ static void pdc_enable_irq(struct dma_ch
+ {
+ struct pch_dma *pd = to_pd(chan->device);
+ u32 val;
++ int pos;
++
++ if (chan->chan_id < 8)
++ pos = chan->chan_id;
++ else
++ pos = chan->chan_id + 8;
+
+ val = dma_readl(pd, CTL2);
+
+ if (enable)
+- val |= 0x1 << chan->chan_id;
++ val |= 0x1 << pos;
+ else
+- val &= ~(0x1 << chan->chan_id);
++ val &= ~(0x1 << pos);
+
+ dma_writel(pd, CTL2, val);
+
+@@ -262,7 +270,7 @@ static void pdc_set_mode(struct dma_chan
+ chan->chan_id, val);
+ }
+
+-static u32 pdc_get_status(struct pch_dma_chan *pd_chan)
++static u32 pdc_get_status0(struct pch_dma_chan *pd_chan)
+ {
+ struct pch_dma *pd = to_pd(pd_chan->chan.device);
+ u32 val;
+@@ -272,9 +280,27 @@ static u32 pdc_get_status(struct pch_dma
+ DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id));
+ }
+
++static u32 pdc_get_status2(struct pch_dma_chan *pd_chan)
++{
++ struct pch_dma *pd = to_pd(pd_chan->chan.device);
++ u32 val;
++
++ val = dma_readl(pd, STS2);
++ return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
++ DMA_STATUS_BITS_PER_CH * (pd_chan->chan.chan_id - 8)));
++}
++
+ static bool pdc_is_idle(struct pch_dma_chan *pd_chan)
+ {
+- if (pdc_get_status(pd_chan) == DMA_STATUS_IDLE)
++ u32 sts;
++
++ if (pd_chan->chan.chan_id < 8)
++ sts = pdc_get_status0(pd_chan);
++ else
++ sts = pdc_get_status2(pd_chan);
++
++
++ if (sts == DMA_STATUS_IDLE)
+ return true;
+ else
+ return false;
+@@ -693,30 +719,45 @@ static irqreturn_t pd_irq(int irq, void
+ struct pch_dma *pd = (struct pch_dma *)devid;
+ struct pch_dma_chan *pd_chan;
+ u32 sts0;
++ u32 sts2;
+ int i;
+- int ret = IRQ_NONE;
++ int ret0 = IRQ_NONE;
++ int ret2 = IRQ_NONE;
+
+ sts0 = dma_readl(pd, STS0);
++ sts2 = dma_readl(pd, STS2);
+
+ dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0);
+
+ for (i = 0; i < pd->dma.chancnt; i++) {
+ pd_chan = &pd->channels[i];
+
+- if (sts0 & DMA_STATUS_IRQ(i)) {
+- if (sts0 & DMA_STATUS_ERR(i))
+- set_bit(0, &pd_chan->err_status);
+-
+- tasklet_schedule(&pd_chan->tasklet);
+- ret = IRQ_HANDLED;
++ if (i < 8) {
++ if (sts0 & DMA_STATUS_IRQ(i)) {
++ if (sts0 & DMA_STATUS0_ERR(i))
++ set_bit(0, &pd_chan->err_status);
++
++ tasklet_schedule(&pd_chan->tasklet);
++ ret0 = IRQ_HANDLED;
++ }
++ } else {
++ if (sts2 & DMA_STATUS_IRQ(i - 8)) {
++ if (sts2 & DMA_STATUS2_ERR(i))
++ set_bit(0, &pd_chan->err_status);
++
++ tasklet_schedule(&pd_chan->tasklet);
++ ret2 = IRQ_HANDLED;
++ }
+ }
+-
+ }
+
+ /* clear interrupt bits in status register */
+- dma_writel(pd, STS0, sts0);
++ if (ret0)
++ dma_writel(pd, STS0, sts0);
++ if (ret2)
++ dma_writel(pd, STS2, sts2);
+
+- return ret;
++ return ret0 | ret2;
+ }
+
+ #ifdef CONFIG_PM
--- /dev/null
+From c43f1508686e8e4746012bf87995085eeb0f5307 Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
+Date: Tue, 11 Oct 2011 21:43:21 +0900
+Subject: pch_dma: Fix suspend issue
+
+From: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
+
+commit c43f1508686e8e4746012bf87995085eeb0f5307 upstream.
+
+Currently, executing suspend/hibernation,
+memory access violation occurs.
+
+In pch_dma_save_regs() called by suspend(),
+you can see the following code.
+
+static void pch_dma_save_regs(struct pch_dma *pd)
+{
+snip...
+ list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
+ pd_chan = to_pd_chan(chan);
+
+ pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
+ pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
+ pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
+ pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
+
+ i++;
+ }
+}
+
+Max loop count is 12 defined at pci_table.
+So, this caused memory access violation.
+
+This patch fixes the issue
+ - Modify array size (MAX_CHAN_NR)
+
+Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
+Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/dma/pch_dma.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/dma/pch_dma.c
++++ b/drivers/dma/pch_dma.c
+@@ -60,7 +60,7 @@
+ #define DMA_DESC_FOLLOW_WITHOUT_IRQ 0x2
+ #define DMA_DESC_FOLLOW_WITH_IRQ 0x3
+
+-#define MAX_CHAN_NR 8
++#define MAX_CHAN_NR 12
+
+ #define DMA_MASK_CTL0_MODE 0x33333333
+ #define DMA_MASK_CTL2_MODE 0x00003333
--- /dev/null
+From ca7fe2db892dcf91b2c72ee352eda4ff867903a7 Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Date: Thu, 17 Nov 2011 16:14:23 +0900
+Subject: pch_dma: Support new device LAPIS Semiconductor ML7831 IOH
+
+From: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+
+commit ca7fe2db892dcf91b2c72ee352eda4ff867903a7 upstream.
+
+ML7831 is companion chip for Intel Atom E6xx series.
+
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/dma/Kconfig | 13 ++++++-------
+ drivers/dma/pch_dma.c | 8 ++++++--
+ 2 files changed, 12 insertions(+), 9 deletions(-)
+
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -200,18 +200,17 @@ config PL330_DMA
+ platform_data for a dma-pl330 device.
+
+ config PCH_DMA
+- tristate "Intel EG20T PCH / OKI Semi IOH(ML7213/ML7223) DMA support"
++ tristate "Intel EG20T PCH / OKI Semi IOH(ML7213/ML7223/ML7831) DMA support"
+ depends on PCI && X86
+ select DMA_ENGINE
+ help
+ Enable support for Intel EG20T PCH DMA engine.
+-
+ This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
+- Output Hub), ML7213 and ML7223.
+- ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is
+- for MP(Media Phone) use.
+- ML7213/ML7223 is companion chip for Intel Atom E6xx series.
+- ML7213/ML7223 is completely compatible for Intel EG20T PCH.
++ Output Hub), ML7213, ML7223 and ML7831.
++ ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
++ for MP(Media Phone) use and ML7831 IOH is for general purpose use.
++ ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
++ ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
+
+ config IMX_SDMA
+ tristate "i.MX SDMA support"
+--- a/drivers/dma/pch_dma.c
++++ b/drivers/dma/pch_dma.c
+@@ -1021,6 +1021,8 @@ static void __devexit pch_dma_remove(str
+ #define PCI_DEVICE_ID_ML7223_DMA2_4CH 0x800E
+ #define PCI_DEVICE_ID_ML7223_DMA3_4CH 0x8017
+ #define PCI_DEVICE_ID_ML7223_DMA4_4CH 0x803B
++#define PCI_DEVICE_ID_ML7831_DMA1_8CH 0x8810
++#define PCI_DEVICE_ID_ML7831_DMA2_4CH 0x8815
+
+ DEFINE_PCI_DEVICE_TABLE(pch_dma_id_table) = {
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
+@@ -1033,6 +1035,8 @@ DEFINE_PCI_DEVICE_TABLE(pch_dma_id_table
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */
++ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA1_8CH), 8}, /* UART */
++ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA2_4CH), 4}, /* SPI */
+ { 0, },
+ };
+
+@@ -1060,7 +1064,7 @@ static void __exit pch_dma_exit(void)
+ module_init(pch_dma_init);
+ module_exit(pch_dma_exit);
+
+-MODULE_DESCRIPTION("Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH "
+- "DMA controller driver");
++MODULE_DESCRIPTION("Intel EG20T PCH / OKI SEMICON ML7213/ML7223/ML7831 IOH"
++ "DMA controller driver");
+ MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>");
+ MODULE_LICENSE("GPL v2");
--- /dev/null
+From 6c4b47d243112e98811ce0da7bbb32cc3857dd1a Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+Date: Wed, 20 Jul 2011 20:17:49 +0900
+Subject: pch_uart: Set PCIe bus number using probe parameter
+
+From: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+
+commit 6c4b47d243112e98811ce0da7bbb32cc3857dd1a upstream.
+
+Currently, PCIe bus number is set as fixed value "2".
+However, PCIe bus number is not always "2".
+This patch sets bus number using probe() parameter.
+
+Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/tty/serial/pch_uart.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/pch_uart.c
++++ b/drivers/tty/serial/pch_uart.c
+@@ -602,7 +602,8 @@ static void pch_request_dma(struct uart_
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+- dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
++ dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
++ PCI_DEVFN(0xa, 0)); /* Get DMA's dev
+ information */
+ /* Set Tx DMA */
+ param = &priv->param_tx;
usb-pch_udc-support-new-device-lapis-semiconductor-ml7831-ioh.patch
acpica-fix-to-allow-region-arguments-to-reference-other-scopes.patch
security-fix-compile-error-in-commoncap.c.patch
+pch_uart-set-pcie-bus-number-using-probe-parameter.patch
+8250_pci-fix-kernel-panic-when-pch_uart-is-disabled.patch
+pch_dma-fix-dma-issue-ch8-ch11.patch
+pch_dma-fix-channel-locking.patch
+pch_dma-fix-ctl-register-access-issue.patch
+pch_dma-fix-suspend-issue.patch
+pch_dma-support-new-device-lapis-semiconductor-ml7831-ioh.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
