--- /dev/null
+From 753872373b599384ac7df809aa61ea12d1c4d5d1 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Thu, 22 Mar 2018 10:11:30 +0100
+Subject: clk: bcm2835: De-assert/assert PLL reset signal when appropriate
+
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+
+commit 753872373b599384ac7df809aa61ea12d1c4d5d1 upstream.
+
+In order to enable a PLL, not only the PLL has to be powered up and
+locked, but you also have to de-assert the reset signal. The last part
+was missing. Add it so PLLs that were not enabled by the FW/bootloader
+can be enabled from Linux.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/bcm/clk-bcm2835.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -891,9 +891,7 @@ static void bcm2835_pll_off(struct clk_h
+ const struct bcm2835_pll_data *data = pll->data;
+
+ spin_lock(&cprman->regs_lock);
+- cprman_write(cprman, data->cm_ctrl_reg,
+- cprman_read(cprman, data->cm_ctrl_reg) |
+- CM_PLL_ANARST);
++ cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) |
+ A2W_PLL_CTRL_PWRDN);
+@@ -929,6 +927,10 @@ static int bcm2835_pll_on(struct clk_hw
+ cpu_relax();
+ }
+
++ cprman_write(cprman, data->a2w_ctrl_reg,
++ cprman_read(cprman, data->a2w_ctrl_reg) |
++ A2W_PLL_CTRL_PRST_DISABLE);
++
+ return 0;
+ }
+
--- /dev/null
+From 9593f4f56cf5d1c443f66660a0c7f01de38f979d Mon Sep 17 00:00:00 2001
+From: Ralph Sennhauser <ralph.sennhauser@gmail.com>
+Date: Wed, 24 May 2017 16:58:52 +0200
+Subject: clk: mvebu: armada-38x: add support for 1866MHz variants
+
+From: Ralph Sennhauser <ralph.sennhauser@gmail.com>
+
+commit 9593f4f56cf5d1c443f66660a0c7f01de38f979d upstream.
+
+The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the
+list of supported CPU frequencies. Also update multiplier and divisor
+for the l2clk and ddrclk.
+
+Noticed by the following warning:
+[ 0.000000] Selected CPU frequency (16) unsupported
+
+Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
+Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/mvebu/armada-38x.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/mvebu/armada-38x.c
++++ b/drivers/clk/mvebu/armada-38x.c
+@@ -49,7 +49,8 @@ static const u32 armada_38x_cpu_frequenc
+ 0, 0, 0, 0,
+ 1066 * 1000 * 1000, 0, 0, 0,
+ 1332 * 1000 * 1000, 0, 0, 0,
+- 1600 * 1000 * 1000,
++ 1600 * 1000 * 1000, 0, 0, 0,
++ 1866 * 1000 * 1000,
+ };
+
+ static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
+@@ -79,7 +80,7 @@ static const int armada_38x_cpu_l2_ratio
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {0, 1}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+@@ -90,7 +91,7 @@ static const int armada_38x_cpu_ddr_rati
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {0, 1}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
--- /dev/null
+From 6a4a4595804548e173f0763a0e7274a3521c59a9 Mon Sep 17 00:00:00 2001
+From: Richard Genoud <richard.genoud@gmail.com>
+Date: Tue, 13 Mar 2018 16:27:02 +0100
+Subject: clk: mvebu: armada-38x: add support for missing clocks
+
+From: Richard Genoud <richard.genoud@gmail.com>
+
+commit 6a4a4595804548e173f0763a0e7274a3521c59a9 upstream.
+
+Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
+or 1333MHz (industrial).
+
+They have also some dip-switches to select a different clock (666, 800,
+1066, 1200).
+
+The funny thing is that the recovery button is on the MPP34 fq selector.
+So, when booting an industrial board with this button down, the frequency
+666MHz is selected (and the kernel didn't boot).
+
+This patch add all the missing clocks.
+
+The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ).
+
+Fixes: 0e85aeced4d6 ("clk: mvebu: add clock support for Armada 380/385")
+Cc: <stable@vger.kernel.org> # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants
+Cc: <stable@vger.kernel.org> # 3.16.x
+
+Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
+Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/mvebu/armada-38x.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/mvebu/armada-38x.c
++++ b/drivers/clk/mvebu/armada-38x.c
+@@ -46,11 +46,11 @@ static u32 __init armada_38x_get_tclk_fr
+ }
+
+ static const u32 armada_38x_cpu_frequencies[] __initconst = {
+- 0, 0, 0, 0,
+- 1066 * 1000 * 1000, 0, 0, 0,
++ 666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
++ 1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
+ 1332 * 1000 * 1000, 0, 0, 0,
+ 1600 * 1000 * 1000, 0, 0, 0,
+- 1866 * 1000 * 1000,
++ 1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
+ };
+
+ static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
+@@ -76,11 +76,11 @@ static const struct coreclk_ratio armada
+ };
+
+ static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
+- {0, 1}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {1, 2}, {0, 1},
++ {1, 2}, {0, 1}, {1, 2}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {1, 2},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+@@ -91,7 +91,7 @@ static const int armada_38x_cpu_ddr_rati
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {7, 15},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
--- /dev/null
+From bbe4b3af9d9e3172fb9aa1f8dcdfaedcb381fc64 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Sat, 24 Feb 2018 13:42:27 +0800
+Subject: iommu/vt-d: Fix a potential memory leak
+
+From: Lu Baolu <baolu.lu@linux.intel.com>
+
+commit bbe4b3af9d9e3172fb9aa1f8dcdfaedcb381fc64 upstream.
+
+A memory block was allocated in intel_svm_bind_mm() but never freed
+in a failure path. This patch fixes this by free it to avoid memory
+leakage.
+
+Cc: Ashok Raj <ashok.raj@intel.com>
+Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
+Cc: <stable@vger.kernel.org> # v4.4+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Fixes: 2f26e0a9c9860 ('iommu/vt-d: Add basic SVM PASID support')
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/iommu/intel-svm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/iommu/intel-svm.c
++++ b/drivers/iommu/intel-svm.c
+@@ -389,6 +389,7 @@ int intel_svm_bind_mm(struct device *dev
+ pasid_max - 1, GFP_KERNEL);
+ if (ret < 0) {
+ kfree(svm);
++ kfree(sdev);
+ goto out;
+ }
+ svm->pasid = ret;
--- /dev/null
+From a04f0017c22453613d5f423326b190c61e3b4f98 Mon Sep 17 00:00:00 2001
+From: Alex Smith <alex.smith@imgtec.com>
+Date: Wed, 28 Mar 2018 18:00:43 -0300
+Subject: mmc: jz4740: Fix race condition in IRQ mask update
+
+From: Alex Smith <alex.smith@imgtec.com>
+
+commit a04f0017c22453613d5f423326b190c61e3b4f98 upstream.
+
+A spinlock is held while updating the internal copy of the IRQ mask,
+but not while writing it to the actual IMASK register. After the lock
+is released, an IRQ can occur before the IMASK register is written.
+If handling this IRQ causes the mask to be changed, when the handler
+returns back to the middle of the first mask update, a stale value
+will be written to the mask register.
+
+If this causes an IRQ to become unmasked that cannot have its status
+cleared by writing a 1 to it in the IREG register, e.g. the SDIO IRQ,
+then we can end up stuck with the same IRQ repeatedly being fired but
+not handled. Normally the MMC IRQ handler attempts to clear any
+unexpected IRQs by writing IREG, but for those that cannot be cleared
+in this way then the IRQ will just repeatedly fire.
+
+This was resulting in lockups after a while of using Wi-Fi on the
+CI20 (GitHub issue #19).
+
+Resolve by holding the spinlock until after the IMASK register has
+been updated.
+
+Cc: stable@vger.kernel.org
+Link: https://github.com/MIPS/CI20_linux/issues/19
+Fixes: 61bfbdb85687 ("MMC: Add support for the controller on JZ4740 SoCs.")
+Tested-by: Mathieu Malaterre <malat@debian.org>
+Signed-off-by: Alex Smith <alex.smith@imgtec.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mmc/host/jz4740_mmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/jz4740_mmc.c
++++ b/drivers/mmc/host/jz4740_mmc.c
+@@ -368,9 +368,9 @@ static void jz4740_mmc_set_irq_enabled(s
+ host->irq_mask &= ~irq;
+ else
+ host->irq_mask |= irq;
+- spin_unlock_irqrestore(&host->lock, flags);
+
+ writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
++ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
+ static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
ib-srp-fix-srp_abort.patch
ib-srp-fix-completion-vector-assignment-algorithm.patch
dmaengine-at_xdmac-fix-rare-residue-corruption.patch
+um-use-posix-ucontext_t-instead-of-struct-ucontext.patch
+iommu-vt-d-fix-a-potential-memory-leak.patch
+mmc-jz4740-fix-race-condition-in-irq-mask-update.patch
+clk-mvebu-armada-38x-add-support-for-1866mhz-variants.patch
+clk-mvebu-armada-38x-add-support-for-missing-clocks.patch
+clk-bcm2835-de-assert-assert-pll-reset-signal-when-appropriate.patch
+thermal-imx-fix-race-condition-in-imx_thermal_probe.patch
+watchdog-f71808e_wdt-fix-wd_en-register-read.patch
--- /dev/null
+From cf1ba1d73a33944d8c1a75370a35434bf146b8a7 Mon Sep 17 00:00:00 2001
+From: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+Date: Fri, 2 Feb 2018 16:17:46 -0200
+Subject: thermal: imx: Fix race condition in imx_thermal_probe()
+
+From: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+
+commit cf1ba1d73a33944d8c1a75370a35434bf146b8a7 upstream.
+
+When device boots with T > T_trip_1 and requests interrupt,
+the race condition takes place. The interrupt comes before
+THERMAL_DEVICE_ENABLED is set. This leads to an attempt to
+reading sensor value from irq and disabling the sensor, based on
+the data->mode field, which expected to be THERMAL_DEVICE_ENABLED,
+but still stays as THERMAL_DEVICE_DISABLED. Afher this issue
+sensor is never re-enabled, as the driver state is wrong.
+
+Fix this problem by setting the 'data' members prior to
+requesting the interrupts.
+
+Fixes: 37713a1e8e4c ("thermal: imx: implement thermal alarm interrupt handling")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/thermal/imx_thermal.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/imx_thermal.c
++++ b/drivers/thermal/imx_thermal.c
+@@ -589,6 +589,9 @@ static int imx_thermal_probe(struct plat
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+
++ data->irq_enabled = true;
++ data->mode = THERMAL_DEVICE_ENABLED;
++
+ ret = devm_request_threaded_irq(&pdev->dev, data->irq,
+ imx_thermal_alarm_irq, imx_thermal_alarm_irq_thread,
+ 0, "imx_thermal", data);
+@@ -600,9 +603,6 @@ static int imx_thermal_probe(struct plat
+ return ret;
+ }
+
+- data->irq_enabled = true;
+- data->mode = THERMAL_DEVICE_ENABLED;
+-
+ return 0;
+ }
+
--- /dev/null
+From 4d1a535b8ec5e74b42dfd9dc809142653b2597f6 Mon Sep 17 00:00:00 2001
+From: Krzysztof Mazur <krzysiek@podlesie.net>
+Date: Wed, 15 Nov 2017 11:12:39 +0100
+Subject: um: Use POSIX ucontext_t instead of struct ucontext
+
+From: Krzysztof Mazur <krzysiek@podlesie.net>
+
+commit 4d1a535b8ec5e74b42dfd9dc809142653b2597f6 upstream.
+
+glibc 2.26 removed the 'struct ucontext' to "improve" POSIX compliance
+and break programs, including User Mode Linux. Fix User Mode Linux
+by using POSIX ucontext_t.
+
+This fixes:
+
+arch/um/os-Linux/signal.c: In function 'hard_handler':
+arch/um/os-Linux/signal.c:163:22: error: dereferencing pointer to incomplete type 'struct ucontext'
+ mcontext_t *mc = &uc->uc_mcontext;
+arch/x86/um/stub_segv.c: In function 'stub_segv_handler':
+arch/x86/um/stub_segv.c:16:13: error: dereferencing pointer to incomplete type 'struct ucontext'
+ &uc->uc_mcontext);
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Krzysztof Mazur <krzysiek@podlesie.net>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/um/os-Linux/signal.c | 2 +-
+ arch/x86/um/stub_segv.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/um/os-Linux/signal.c
++++ b/arch/um/os-Linux/signal.c
+@@ -140,7 +140,7 @@ static void (*handlers[_NSIG])(int sig,
+
+ static void hard_handler(int sig, siginfo_t *si, void *p)
+ {
+- struct ucontext *uc = p;
++ ucontext_t *uc = p;
+ mcontext_t *mc = &uc->uc_mcontext;
+ unsigned long pending = 1UL << sig;
+
+--- a/arch/x86/um/stub_segv.c
++++ b/arch/x86/um/stub_segv.c
+@@ -10,7 +10,7 @@
+ void __attribute__ ((__section__ (".__syscall_stub")))
+ stub_segv_handler(int sig, siginfo_t *info, void *p)
+ {
+- struct ucontext *uc = p;
++ ucontext_t *uc = p;
+
+ GET_FAULTINFO_FROM_MC(*((struct faultinfo *) STUB_DATA),
+ &uc->uc_mcontext);
--- /dev/null
+From 977f6f68331f94bb72ad84ee96b7b87ce737d89d Mon Sep 17 00:00:00 2001
+From: Igor Pylypiv <igor.pylypiv@gmail.com>
+Date: Tue, 6 Mar 2018 23:47:25 -0800
+Subject: watchdog: f71808e_wdt: Fix WD_EN register read
+
+From: Igor Pylypiv <igor.pylypiv@gmail.com>
+
+commit 977f6f68331f94bb72ad84ee96b7b87ce737d89d upstream.
+
+F71808FG_FLAG_WD_EN defines bit position, not a bitmask
+
+Signed-off-by: Igor Pylypiv <igor.pylypiv@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/watchdog/f71808e_wdt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/watchdog/f71808e_wdt.c
++++ b/drivers/watchdog/f71808e_wdt.c
+@@ -450,7 +450,7 @@ static bool watchdog_is_running(void)
+
+ is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0))
+ && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF)
+- & F71808FG_FLAG_WD_EN);
++ & BIT(F71808FG_FLAG_WD_EN));
+
+ superio_exit(watchdog.sioaddr);
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
