gdb_assert (regno != -1);
gdb_assert (tdep->tls_register_count > 0);
- uint64_t tpidrs[tdep->tls_register_count];
- memset(tpidrs, 0, sizeof(tpidrs));
+ std::vector<uint64_t> tpidrs (tdep->tls_register_count);
struct iovec iovec;
- iovec.iov_base = tpidrs;
- iovec.iov_len = sizeof (tpidrs);
+ iovec.iov_base = tpidrs.data ();
+ iovec.iov_len = tpidrs.size () * sizeof (tpidrs[0]);
int tid = get_ptrace_pid (regcache->ptid ());
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
gdb_assert (regno != -1);
gdb_assert (tdep->tls_register_count > 0);
- uint64_t tpidrs[tdep->tls_register_count];
- memset(tpidrs, 0, sizeof(tpidrs));
+ std::vector<uint64_t> tpidrs (tdep->tls_register_count);
for (int i = 0; i < tdep->tls_register_count; i++)
{
}
struct iovec iovec;
- iovec.iov_base = &tpidrs;
- iovec.iov_len = sizeof (tpidrs);
+ iovec.iov_base = tpidrs.data ();
+ iovec.iov_len = tpidrs.size () * sizeof (tpidrs[0]);
int tid = get_ptrace_pid (regcache->ptid ());
if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
}
else
{
- gdb_byte za_zeroed[za_bytes];
- memset (za_zeroed, 0, za_bytes);
+ gdb::byte_vector za_zeroed (za_bytes, 0);
regcache->raw_supply (tdep->sme_za_regnum, za_zeroed);
}
}
{
int regnum = AARCH64_V0_REGNUM + info->nsrn;
/* Enough space for a full vector register. */
- gdb_byte reg[register_size (gdbarch, regnum)];
- gdb_assert (len <= sizeof (reg));
+ gdb::byte_vector reg (register_size (gdbarch, regnum), 0);
+ gdb_assert (len <= reg.size ());
info->argnum++;
info->nsrn++;
- memset (reg, 0, sizeof (reg));
/* PCS C.1, the argument is allocated to the least significant
bits of V register. */
- memcpy (reg, buf, len);
+ memcpy (reg.data (), buf, len);
regcache->cooked_write (regnum, reg);
aarch64_debug_printf ("arg %d in %s", info->argnum,
{
int regno = AARCH64_V0_REGNUM + i;
/* Enough space for a full vector register. */
- gdb_byte buf[register_size (gdbarch, regno)];
- gdb_assert (len <= sizeof (buf));
+ gdb::byte_vector buf (register_size (gdbarch, regno));
+ gdb_assert (len <= buf.size ());
aarch64_debug_printf
("read HFA or HVA return value element %d from %s",
regs->cooked_read (regno, buf);
- memcpy (valbuf, buf, len);
+ memcpy (valbuf, buf.data (), len);
valbuf += len;
}
}
{
int regno = AARCH64_V0_REGNUM + i;
/* Enough space for a full vector register. */
- gdb_byte tmpbuf[register_size (gdbarch, regno)];
- gdb_assert (len <= sizeof (tmpbuf));
+ gdb::byte_vector tmpbuf (register_size (gdbarch, regno));
+ gdb_assert (len <= tmpbuf.size ());
aarch64_debug_printf
("write HFA or HVA return value element %d to %s",
original contents of the register before overriding it with a new
value that has a potential size <= 16 bytes. */
regs->cooked_read (regno, tmpbuf);
- memcpy (tmpbuf, valbuf,
+ memcpy (tmpbuf.data (), valbuf,
len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
regs->cooked_write (regno, tmpbuf);
valbuf += len;
{
unsigned raw_regnum = AARCH64_V0_REGNUM + regnum_offset;
- /* Enough space for a full vector register. */
- int raw_reg_size = register_size (gdbarch, raw_regnum);
- gdb_byte raw_buf[raw_reg_size];
- static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
+ /* Enough space for a full vector register.
- /* Ensure the register buffer is zero, we want gdb writes of the
+ Ensure the register buffer is zero, we want gdb writes of the
various 'scalar' pseudo registers to behavior like architectural
writes, register width bytes are written the remainder are set to
zero. */
- memset (raw_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
+ gdb::byte_vector raw_buf (register_size (gdbarch, raw_regnum), 0);
+ static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
- gdb::array_view<gdb_byte> raw_view (raw_buf, raw_reg_size);
+ gdb::array_view<gdb_byte> raw_view (raw_buf);
copy (buf, raw_view.slice (0, buf.size ()));
put_frame_register (next_frame, raw_regnum, raw_view);
}
if (have_ptrace_getregset == TRIBOOL_TRUE)
{
- char xstateregs[tdep->xsave_layout.sizeof_xsave];
- struct iovec iov;
-
/* Pre-4.14 kernels have a bug (fixed by commit 0852b374173b
"x86/fpu: Add FPU state copying quirk to handle XRSTOR failure on
Intel Skylake CPUs") that sometimes causes the mxcsr location in
xstateregs not to be copied by PTRACE_GETREGSET. Make sure that
the location is at least initialized with a defined value. */
- memset (xstateregs, 0, sizeof (xstateregs));
- iov.iov_base = xstateregs;
- iov.iov_len = sizeof (xstateregs);
+ gdb::byte_vector xstateregs (tdep->xsave_layout.sizeof_xsave, 0);
+ struct iovec iov;
+
+ iov.iov_base = xstateregs.data ();
+ iov.iov_len = xstateregs.size ();
if (ptrace (PTRACE_GETREGSET, tid,
(unsigned int) NT_X86_XSTATE, (long) &iov) < 0)
perror_with_name (_("Couldn't get extended state status"));
- amd64_supply_xsave (regcache, -1, xstateregs);
+ amd64_supply_xsave (regcache, -1, xstateregs.data ());
}
else
{
if (have_ptrace_getregset == TRIBOOL_TRUE)
{
- char xstateregs[tdep->xsave_layout.sizeof_xsave];
+ gdb::byte_vector xstateregs (tdep->xsave_layout.sizeof_xsave);
struct iovec iov;
- iov.iov_base = xstateregs;
- iov.iov_len = sizeof (xstateregs);
+ iov.iov_base = xstateregs.data ();
+ iov.iov_len = xstateregs.size ();
if (ptrace (PTRACE_GETREGSET, tid,
(unsigned int) NT_X86_XSTATE, (long) &iov) < 0)
perror_with_name (_("Couldn't get extended state status"));
- amd64_collect_xsave (regcache, regnum, xstateregs, 0);
+ amd64_collect_xsave (regcache, regnum, xstateregs.data (), 0);
if (ptrace (PTRACE_SETREGSET, tid,
(unsigned int) NT_X86_XSTATE, (long) &iov) < 0)
{
LONGEST tls_index = fbsd_get_tls_index (gdbarch, lm_addr);
- gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
- if (target_read_memory (dtv_addr, buf, sizeof buf) != 0)
+ gdb::byte_vector buf (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
+ if (target_read_memory (dtv_addr, buf.data (), buf.size ()) != 0)
throw_error (TLS_GENERIC_ERROR,
_("Cannot find thread-local variables on this target"));
const struct builtin_type *builtin = builtin_type (gdbarch);
- CORE_ADDR addr = gdbarch_pointer_to_address (gdbarch,
- builtin->builtin_data_ptr, buf);
+ CORE_ADDR addr
+ = gdbarch_pointer_to_address (gdbarch, builtin->builtin_data_ptr,
+ buf.data ());
addr += (tls_index + 1) * builtin->builtin_data_ptr->length ();
- if (target_read_memory (addr, buf, sizeof buf) != 0)
+ if (target_read_memory (addr, buf.data (), buf.size ()) != 0)
throw_error (TLS_GENERIC_ERROR,
_("Cannot find thread-local variables on this target"));
- addr = gdbarch_pointer_to_address (gdbarch, builtin->builtin_data_ptr, buf);
+ addr = gdbarch_pointer_to_address (gdbarch, builtin->builtin_data_ptr,
+ buf.data ());
return addr + offset;
}
{
struct gdbarch *gdbarch = regcache->arch ();
const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
- char xstateregs[tdep->xsave_layout.sizeof_xsave];
+ gdb::byte_vector xstateregs (tdep->xsave_layout.sizeof_xsave);
struct iovec iov;
if (have_ptrace_getregset != TRIBOOL_TRUE)
return 0;
- iov.iov_base = xstateregs;
- iov.iov_len = sizeof(xstateregs);
+ iov.iov_base = xstateregs.data ();
+ iov.iov_len = xstateregs.size ();
if (ptrace (PTRACE_GETREGSET, tid, (unsigned int) NT_X86_XSTATE,
&iov) < 0)
perror_with_name (_("Couldn't read extended state status"));
- i387_supply_xsave (regcache, -1, xstateregs);
+ i387_supply_xsave (regcache, -1, xstateregs.data ());
return 1;
}
{
struct gdbarch *gdbarch = regcache->arch ();
const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
- char xstateregs[tdep->xsave_layout.sizeof_xsave];
+ gdb::byte_vector xstateregs (tdep->xsave_layout.sizeof_xsave);
struct iovec iov;
if (have_ptrace_getregset != TRIBOOL_TRUE)
return 0;
-
- iov.iov_base = xstateregs;
- iov.iov_len = sizeof(xstateregs);
+
+ iov.iov_base = xstateregs.data ();
+ iov.iov_len = xstateregs.size ();
if (ptrace (PTRACE_GETREGSET, tid, (unsigned int) NT_X86_XSTATE,
&iov) < 0)
perror_with_name (_("Couldn't read extended state status"));
- i387_collect_xsave (regcache, regno, xstateregs, 0);
+ i387_collect_xsave (regcache, regno, xstateregs.data (), 0);
if (ptrace (PTRACE_SETREGSET, tid, (unsigned int) NT_X86_XSTATE,
(int) &iov) < 0)
loongarch_fetch_instruction (CORE_ADDR pc)
{
size_t insn_len = loongarch_insn_length (0);
- gdb_byte buf[insn_len];
+ gdb::byte_vector buf (insn_len);
int err;
- err = target_read_memory (pc, buf, insn_len);
+ err = target_read_memory (pc, buf.data (), insn_len);
if (err)
memory_error (TARGET_XFER_E_IO, pc);
- return extract_unsigned_integer (buf, insn_len, BFD_ENDIAN_LITTLE);
+ return extract_unsigned_integer (buf.data (), insn_len, BFD_ENDIAN_LITTLE);
}
/* Return TRUE if INSN is a unconditional branch instruction, otherwise return FALSE. */
and the signed integer scalars are sign-extended. */
if (writebuf)
{
- gdb_byte buf[regsize];
+ gdb::byte_vector buf (regsize);
if (type->is_unsigned ())
{
- ULONGEST data = extract_unsigned_integer (writebuf, len, BFD_ENDIAN_LITTLE);
- store_unsigned_integer (buf, regsize, BFD_ENDIAN_LITTLE, data);
+ ULONGEST data = extract_unsigned_integer (writebuf, len,
+ BFD_ENDIAN_LITTLE);
+ store_unsigned_integer (buf.data (), regsize,
+ BFD_ENDIAN_LITTLE, data);
}
else
{
- LONGEST data = extract_signed_integer (writebuf, len, BFD_ENDIAN_LITTLE);
- store_signed_integer (buf, regsize, BFD_ENDIAN_LITTLE, data);
+ LONGEST data
+ = extract_signed_integer (writebuf, len, BFD_ENDIAN_LITTLE);
+ store_signed_integer (buf.data (), regsize, BFD_ENDIAN_LITTLE,
+ data);
}
- loongarch_xfer_reg (regcache, a0, regsize, nullptr, buf, 0);
+
+ loongarch_xfer_reg (regcache, a0, regsize, nullptr, buf.data (),
+ 0);
}
else
loongarch_xfer_reg (regcache, a0, len, readbuf, nullptr, 0);
CORE_ADDR jb_addr;
struct gdbarch *gdbarch = get_frame_arch (frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
+ gdb::byte_vector buf (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
if (target_read_memory ((jb_addr
+ MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE),
- buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
+ buf.data (),
+ gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
return 0;
- *pc = extract_unsigned_integer (buf,
+ *pc = extract_unsigned_integer (buf.data (),
gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
byte_order);
if (ntags == 0)
return true;
- gdb_byte tagbuf[ntags];
+ gdb::byte_vector tagbuf (ntags);
struct iovec iovec;
- iovec.iov_base = tagbuf;
+ iovec.iov_base = tagbuf.data ();
iovec.iov_len = ntags;
tags.clear ();
else
{
size_t za_bytes = header->vl * header->vl;
- gdb_byte za_zeroed[za_bytes];
- memset (za_zeroed, 0, za_bytes);
+ gdb::byte_vector za_zeroed (za_bytes, 0);
reg_buf->raw_supply (za_regnum, za_zeroed);
}
bool has_za_state = aarch64_has_za_state (tid);
size_t za_bytes = sve_vl_from_vg (old_svg) * sve_vl_from_vg (old_svg);
- gdb_byte za_zeroed[za_bytes];
- memset (za_zeroed, 0, za_bytes);
+ gdb::byte_vector za_zeroed (za_bytes, 0);
/* If the streaming vector length changed, zero out the contents of ZA in
the register cache. Otherwise, we will need to update the ZA contents
/* When we update svg, we don't automatically initialize the ZA buffer. If
we have no ZA state and the ZA register contents in the register cache are
zero, just return and leave the ZA register cache contents as zero. */
- if (!has_za_state
- && reg_buf->raw_compare (za_regnum, za_zeroed, 0))
+ if (!has_za_state && reg_buf->raw_compare (za_regnum, za_zeroed.data (), 0))
{
/* No ZA state in the thread or in the register cache. This was likely
just an adjustment of the streaming vector length. Let this fall
need to initialize the ZA data through ptrace. First we initialize
all the bytes of ZA to zero. */
if (!has_za_state
- && !reg_buf->raw_compare (za_regnum, za_zeroed, 0))
+ && !reg_buf->raw_compare (za_regnum, za_zeroed.data (), 0))
aarch64_initialize_za_regset (tid);
/* From this point onwards, it is assumed we have a ZA payload in
if (regnum == tdep->fflags_regnum || regnum == tdep->frm_regnum)
{
int fcsr_regnum = RISCV_CSR_FCSR_REGNUM;
- gdb_byte raw_buf[register_size (gdbarch, fcsr_regnum)];
+ gdb::byte_vector raw_buf (register_size (gdbarch, fcsr_regnum));
regcache->raw_read (fcsr_regnum, raw_buf);
for (int i = 0; i < info->all_image.count; i++)
{
CORE_ADDR iinfo = info->all_image.info + i * image_info_size;
- gdb_byte buf[image_info_size];
+ gdb::byte_vector buf (image_info_size);
CORE_ADDR load_addr;
CORE_ADDR path_addr;
struct mach_o_header_external hdr;
unsigned long hdr_val;
/* Read image info from inferior. */
- if (target_read_memory (iinfo, buf, image_info_size))
+ if (target_read_memory (iinfo, buf.data (), image_info_size))
break;
- load_addr = extract_typed_address (buf, ptr_type);
- path_addr = extract_typed_address (buf + ptr_len, ptr_type);
+ load_addr = extract_typed_address (buf.data (), ptr_type);
+ path_addr = extract_typed_address (buf.data () + ptr_len, ptr_type);
/* Read Mach-O header from memory. */
if (target_read_memory (load_addr, (gdb_byte *) &hdr, sizeof (hdr) - 4))
for (i = 0; i < info->all_image.count; i++)
{
CORE_ADDR iinfo = info->all_image.info + i * image_info_size;
- gdb_byte buf[image_info_size];
+ gdb::byte_vector buf (image_info_size);
CORE_ADDR load_addr;
/* Read image info from inferior. */
- if (target_read_memory (iinfo, buf, image_info_size))
+ if (target_read_memory (iinfo, buf.data (), image_info_size))
break;
- load_addr = extract_typed_address (buf, ptr_type);
+ load_addr = extract_typed_address (buf.data (), ptr_type);
if (darwin_validate_exec_header (load_addr) == load_addr)
return load_addr;
}
else
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- gdb_byte buf[slot_size];
+ gdb::byte_vector buf (slot_size);
- if (target_read_memory (addr + offs, buf, sizeof buf) == 0)
+ if (target_read_memory (addr + offs, buf.data (), buf.size ())
+ == 0)
{
LONGEST val
- = extract_unsigned_integer (buf, sizeof buf, byte_order);
+ = extract_unsigned_integer (buf.data (), buf.size (),
+ byte_order);
trad_frame_set_reg_value (this_trad_cache, regno, val);
}
}