re PR target/58361 (Wrong floating point code generated for ARM target)

	PR target/58361
	* arm/vfp.md (combine_vcvt_f32_<FCVTI32typename>): Fix pattern to
	support conditional execution.
	(combine_vcvt_f64_<FCVTI32typename>): Likewise.

From-SVN: r202475

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bf0a9b46d2f4785a9b2d2602e6be0df7b86a7363..78282ea70e2e915bf030fad32435ef35267f1983 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-09-10  Richard Earnshaw  <rearnsha@arm.com>
+
+       PR target/58361
+       * arm/vfp.md (combine_vcvt_f32_<FCVTI32typename>): Fix pattern to
+       support conditional execution.
+       (combine_vcvt_f64_<FCVTI32typename>): Likewise.
+
 2013-09-10  Vladimir Makarov  <vmakarov@redhat.com>
 
        * lra.c (lra): Clear lra_optional_reload_pseudos before every

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 9318e49d9ea6fcbd4783c749aa6db43ac7fa8265..0b10c130d70d05daa47f2970d8c3e8c6c42a8a69 100644 (file)
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1217,19 +1217,20 @@
    (set_attr "type" "fcmpd")]
 )
 
-;; Fixed point to floating point conversions. 
+;; Fixed point to floating point conversions.
 (define_code_iterator FCVT [unsigned_float float])
 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
 
 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
   [(set (match_operand:SF 0 "s_register_operand" "=t")
        (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
-                (match_operand 2 
+                (match_operand 2
                        "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
-  "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
- [(set_attr "predicable" "no")
-  (set_attr "type" "f_cvti2f")]
+  "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "f_cvti2f")]
 )
 
 ;; Not the ideal way of implementing this. Ideally we would be able to split
@@ -1237,17 +1238,19 @@
 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
   [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
        (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
-                (match_operand 2 
+                (match_operand 2
                     "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math 
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
   && !TARGET_VFP_SINGLE"
   "@
-  vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
-  vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
-  vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
- [(set_attr "predicable" "no")
-  (set_attr "type" "f_cvti2f")
-  (set_attr "length" "8")]
+  vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
+  vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
+  vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
+  [(set_attr "predicable" "yes")
+   (set_attr "ce_count" "2")
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "f_cvti2f")
+   (set_attr "length" "8")]
 )
 
 ;; Store multiple insn used in function prologue.