cxl/pci: Remove duplicate host_bridge->native_aer checking

cxl_dport_init_ras_reporting() already checks host_bridge->native_aer
before invoking cxl_disable_rch_root_ints(), so
cxl_disable_rch_root_ints() does not need to check it again.

Signed-off-by: Li Ming <ming4.li@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240830061308.2327065-3-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index ccd46843e1e71296d69a42f51b5dedcb241ce2e6..5e5c24eed545b6d5cde05090c02ac3aa88445e1e 100644 (file)
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -800,14 +800,11 @@ static void cxl_dport_map_ras(struct cxl_dport *dport)
 static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
 {
        void __iomem *aer_base = dport->regs.dport_aer;
-       struct pci_host_bridge *bridge;
        u32 aer_cmd_mask, aer_cmd;
 
        if (!aer_base)
                return;
 
-       bridge = to_pci_host_bridge(dport->dport_dev);
-
        /*
         * Disable RCH root port command interrupts.
         * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
@@ -816,14 +813,12 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
         * the root cmd register's interrupts is required. But, PCI spec
         * shows these are disabled by default on reset.
         */
-       if (bridge->native_aer) {
-               aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
-                               PCI_ERR_ROOT_CMD_NONFATAL_EN |
-                               PCI_ERR_ROOT_CMD_FATAL_EN);
-               aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
-               aer_cmd &= ~aer_cmd_mask;
-               writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
-       }
+       aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
+                       PCI_ERR_ROOT_CMD_NONFATAL_EN |
+                       PCI_ERR_ROOT_CMD_FATAL_EN);
+       aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
+       aer_cmd &= ~aer_cmd_mask;
+       writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
 }
 
 /**