clk: eyeq: require clock index with phandle in all cases

We used to let compatibles with a single clock exposed to not have
a cell. Switch away from that and enforce a cell in all cases.

This is done at the same time as some compatibles
(mobileye,eyeq6h-{central,west}-olb) go from one to more clocks
exposed. Let's do the same switch and avoid future devicetree
work if/when others follow.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-4-84cfefb3f485@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 77f1afb020a0247b9d73b59a88845b21a0d83b5e..ed4dab303d9121cd8bf453448b4c86547ea9244c 100644 (file)
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -367,11 +367,7 @@ static int eqc_probe(struct platform_device *pdev)
 
        eqc_probe_init_divs(dev, data, base, cells);
 
-       /* When providing a single clock, require no cell. */
-       if (clk_count == 1)
-               return of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]);
-       else
-               return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
+       return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
 }
 
 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
@@ -637,11 +633,7 @@ static void __init eqc_early_init(struct device_node *np,
                }
        }
 
-       /* When providing a single clock, require no cell. */
-       if (clk_count == 1)
-               ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]);
-       else
-               ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
+       ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
        if (ret) {
                pr_err("failed registering clk provider: %d\n", ret);
                goto err;