5.15-stable patches

added patches:
	cpufreq-intel_pstate-itmt-support-for-overclocked-system.patch

diff --git a/queue-5.15/cpufreq-intel_pstate-itmt-support-for-overclocked-system.patch b/queue-5.15/cpufreq-intel_pstate-itmt-support-for-overclocked-system.patch
new file mode 100644 (file)
index 0000000..2e5f4d7
--- /dev/null
+++ b/queue-5.15/cpufreq-intel_pstate-itmt-support-for-overclocked-system.patch
@@ -0,0 +1,57 @@
+From 03c83982a0278207709143ba78c5a470179febee Mon Sep 17 00:00:00 2001
+From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+Date: Thu, 18 Nov 2021 21:18:01 -0800
+Subject: cpufreq: intel_pstate: ITMT support for overclocked system
+
+From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+
+commit 03c83982a0278207709143ba78c5a470179febee upstream.
+
+On systems with overclocking enabled, CPPC Highest Performance can be
+hard coded to 0xff. In this case even if we have cores with different
+highest performance, ITMT can't be enabled as the current implementation
+depends on CPPC Highest Performance.
+
+On such systems we can use MSR_HWP_CAPABILITIES maximum performance field
+when CPPC.Highest Performance is 0xff.
+
+Due to legacy reasons, we can't solely depend on MSR_HWP_CAPABILITIES as
+in some older systems CPPC Highest Performance is the only way to identify
+different performing cores.
+
+Reported-by: Michael Larabel <Michael@MichaelLarabel.com>
+Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+Tested-by: Michael Larabel <Michael@MichaelLarabel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Dimitri John Ledkov <dimitri.ledkov@canonical.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/cpufreq/intel_pstate.c |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/cpufreq/intel_pstate.c
++++ b/drivers/cpufreq/intel_pstate.c
+@@ -335,6 +335,8 @@ static void intel_pstste_sched_itmt_work
+ 
+ static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
+ 
++#define CPPC_MAX_PERF U8_MAX
++
+ static void intel_pstate_set_itmt_prio(int cpu)
+ {
+       struct cppc_perf_caps cppc_perf;
+@@ -346,6 +348,14 @@ static void intel_pstate_set_itmt_prio(i
+               return;
+ 
+       /*
++       * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
++       * In this case we can't use CPPC.highest_perf to enable ITMT.
++       * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
++       */
++      if (cppc_perf.highest_perf == CPPC_MAX_PERF)
++              cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
++
++      /*
+        * The priorities can be set regardless of whether or not
+        * sched_set_itmt_support(true) has been called and it is valid to
+        * update them at any time after it has been called.

diff --git a/queue-5.15/series b/queue-5.15/series
index 55c7228739802c7adb634a4eb6aa101efc5b1515..f3601d087d2ab5a8d314ea10585934177b317440 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -178,3 +178,4 @@ drm-i915-sunset-igpu-legacy-mmap-support-based-on-graphics_ver_full.patch
 cpu-hotplug-remove-the-cpu-member-of-cpuhp_cpu_state.patch
 soc-qcom-aoss-fix-missing-put_device-call-in-qmp_get.patch
 net-ipa-fix-a-build-dependency.patch
+cpufreq-intel_pstate-itmt-support-for-overclocked-system.patch