drm/i915: s/disable_lp_wm/disable_cxsr/

The ilk+ disable_lp_wm boolean has the exact same role as
disable_cxsr for gmch platforms. The documentation also
still talks about CxSR on ilk+ even theough the way you
control it has now change to involve toggling the LP watermarks.
Get rid of disable_lp_wm and just use disable_cxsr for ilk+
as well.

TODO: Unify even more to not have any gmch vs. ilk+
      details in high level modeset code...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240916162413.8555-7-ville.syrjala@linux.intel.com
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 999fc085af286e88fc1d9573be93e0e157bd2634..5b5f2875ea402f5a83412b73bc913fcda1444a08 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -3397,7 +3397,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
        dev_priv->display.wm.hw = *results;
 }
 
-bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
+bool ilk_disable_cxsr(struct drm_i915_private *dev_priv)
 {
        return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h b/drivers/gpu/drm/i915/display/i9xx_wm.h
index de0920730ab2c14f1abfbc00d5e43965046e4e64..06ac37c6c94b5b986be36cfb8d6f8f1ee5c4ce9b 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_wm.h
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.h
@@ -13,12 +13,12 @@ struct intel_crtc_state;
 struct intel_plane_state;
 
 #ifdef I915
-bool ilk_disable_lp_wm(struct drm_i915_private *i915);
+bool ilk_disable_cxsr(struct drm_i915_private *i915);
 void ilk_wm_sanitize(struct drm_i915_private *i915);
 bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);
 void i9xx_wm_init(struct drm_i915_private *i915);
 #else
-static inline bool ilk_disable_lp_wm(struct drm_i915_private *i915)
+static inline bool ilk_disable_cxsr(struct drm_i915_private *i915)
 {
        return false;
 }

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 12d6ed940751427f94b3c9a504fc308d85fabfb6..6cac26af128c72f0e6c851fdc3551632a8da26d2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -266,7 +266,6 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
        crtc_state->update_pipe = false;
        crtc_state->update_m_n = false;
        crtc_state->update_lrr = false;
-       crtc_state->disable_lp_wm = false;
        crtc_state->disable_cxsr = false;
        crtc_state->update_wm_pre = false;
        crtc_state->update_wm_post = false;

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b2cc7f1dee0c4fb9c3dbd664569db8648d8e73b1..3505a5b52eb9babb58f059ad1a8995746278c7bb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -471,9 +471,9 @@ static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state
        return old_ctl != new_ctl;
 }
 
-static bool ilk_must_disable_lp_wm(const struct intel_crtc_state *new_crtc_state,
-                                  const struct intel_plane_state *old_plane_state,
-                                  const struct intel_plane_state *new_plane_state)
+static bool ilk_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
+                                 const struct intel_plane_state *old_plane_state,
+                                 const struct intel_plane_state *new_plane_state)
 {
        struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
        bool old_visible = old_plane_state->uapi.visible;
@@ -588,8 +588,8 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
                new_crtc_state->disable_cxsr = true;
 
        if ((IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) &&
-           ilk_must_disable_lp_wm(new_crtc_state, old_plane_state, new_plane_state))
-               new_crtc_state->disable_lp_wm = true;
+           ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
+               new_crtc_state->disable_cxsr = true;
 
        if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
                new_crtc_state->do_async_flip = true;

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ca98ecbf24a98b2e279e35db452aa1f9b85d7827..f7667931f9d945666f2c1e5f006994b8bba3c92d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1324,8 +1324,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
         *
         * WaCxSRDisabledForSpriteScaling:ivb
         */
-       if (old_crtc_state->hw.active &&
-           new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
+       if (!HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
+           new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))
                intel_crtc_wait_for_next_vblank(crtc);
 
        /*

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b1eed230285a04f00c03447cab49e6ea0c1badfb..7ff97e5b83dd5e8d07d307ef1a27c1008fae25ea 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1143,9 +1143,6 @@ struct intel_crtc_state {
        /* w/a for waiting 2 vblanks during crtc enable */
        enum pipe hsw_workaround_pipe;
 
-       /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
-       bool disable_lp_wm;
-
        struct intel_crtc_wm_state wm;
 
        int min_cdclk[I915_MAX_PLANES];