]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
add hpt374 udma fix
authorChris Wright <chrisw@sous-sol.org>
Tue, 12 Jun 2007 17:09:57 +0000 (10:09 -0700)
committerChris Wright <chrisw@sous-sol.org>
Tue, 12 Jun 2007 17:09:57 +0000 (10:09 -0700)
queue-2.6.21/hpt366-disallow-ultra133-for-hpt374.patch [new file with mode: 0644]
queue-2.6.21/series

diff --git a/queue-2.6.21/hpt366-disallow-ultra133-for-hpt374.patch b/queue-2.6.21/hpt366-disallow-ultra133-for-hpt374.patch
new file mode 100644 (file)
index 0000000..9116283
--- /dev/null
@@ -0,0 +1,52 @@
+From 278978e953a35a2ddf27f197003b29da54e31908 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
+Date: Fri, 8 Jun 2007 15:14:32 +0200
+Subject: hpt366: disallow Ultra133 for HPT374
+
+Eliminate UltraATA/133 support for HPT374 -- the chip isn't capable of this mode
+according to the manual, and doesn't even seem to tolerate 66 MHz DPLL clock...
+
+Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
+Cc: Geller Sandor <wildy@petra.hos.u-szeged.hu>
+Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
+Signed-off-by: Chris Wright <chrisw@sous-sol.org>
+---
+ drivers/ide/pci/hpt366.c |    8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- linux-2.6.21.5.orig/drivers/ide/pci/hpt366.c
++++ linux-2.6.21.5/drivers/ide/pci/hpt366.c
+@@ -1,5 +1,5 @@
+ /*
+- * linux/drivers/ide/pci/hpt366.c             Version 1.03    May 4, 2007
++ * linux/drivers/ide/pci/hpt366.c             Version 1.04    Jun 4, 2007
+  *
+  * Copyright (C) 1999-2003            Andre Hedrick <andre@linux-ide.org>
+  * Portions Copyright (C) 2001                Sun Microsystems, Inc.
+@@ -106,7 +106,8 @@
+  *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
+  *   frequency
+  * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
+- *   anything  newer than HPT370/A
++ *   anything  newer than HPT370/A (except HPT374 that is not capable of this
++ *   mode according to the manual)
+  * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
+  *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
+  *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
+@@ -365,7 +366,6 @@ static u32 sixty_six_base_hpt37x[] = {
+ };
+ #define HPT366_DEBUG_DRIVE_INFO               0
+-#define HPT374_ALLOW_ATA133_6         1
+ #define HPT371_ALLOW_ATA133_6         1
+ #define HPT302_ALLOW_ATA133_6         1
+ #define HPT372_ALLOW_ATA133_6         1
+@@ -450,7 +450,7 @@ static struct hpt_info hpt370a __devinit
+ static struct hpt_info hpt374 __devinitdata = {
+       .chip_type      = HPT374,
+-      .max_mode       = HPT374_ALLOW_ATA133_6 ? 4 : 3,
++      .max_mode       = 3,
+       .dpll_clk       = 48,
+       .settings       = hpt37x_settings
+ };
index 04a0a24d5714f4067bf63d17ca653283d5b2b3a6..b1b9a92bfec21e4a67796dbd4b3c226b5bf9526f 100644 (file)
@@ -3,3 +3,4 @@ fix-show_mem-x86_64-sparsemem.patch
 rt-mutex-fix-stale-return-value.patch
 rt-mutex-fix-chain-walk-early-wakeup-bug.patch
 pi-futex-fix-exit-races-and-locking-problems.patch
+hpt366-disallow-ultra133-for-hpt374.patch