]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: rockchip: Add HDMI0 node to rk3588
authorCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Sat, 19 Oct 2024 10:12:10 +0000 (13:12 +0300)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 22 Oct 2024 14:10:26 +0000 (16:10 +0200)
Add support for the HDMI0 output port found on RK3588 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi

index d97d84b888375c5a5a480255c92790ad511befb7..bef5847953110bd0fd9a72290869f7feea5b848b 100644 (file)
                status = "disabled";
        };
 
+       hdmi0: hdmi@fde80000 {
+               compatible = "rockchip,rk3588-dw-hdmi-qp";
+               reg = <0x0 0xfde80000 0x0 0x20000>;
+               clocks = <&cru PCLK_HDMITX0>,
+                        <&cru CLK_HDMITX0_EARC>,
+                        <&cru CLK_HDMITX0_REF>,
+                        <&cru MCLK_I2S5_8CH_TX>,
+                        <&cru CLK_HDMIHDP0>,
+                        <&cru HCLK_VO1>;
+               clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "avp", "cec", "earc", "main", "hpd";
+               phys = <&hdptxphy_hdmi0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+                            &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+               power-domains = <&power RK3588_PD_VO1>;
+               resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+               reset-names = "ref", "hdp";
+               rockchip,grf = <&sys_grf>;
+               rockchip,vo-grf = <&vo1_grf>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       hdmi0_in: port@0 {
+                               reg = <0>;
+                       };
+
+                       hdmi0_out: port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
        qos_gpu_m0: qos@fdf35000 {
                compatible = "rockchip,rk3588-qos", "syscon";
                reg = <0x0 0xfdf35000 0x0 0x20>;