drm/i915/bw: make struct intel_bw_state opaque

With all the code touching struct intel_bw_state moved inside
intel_bw.c, we move the struct definition there too, and make the type
opaque. to_intel_bw_state() needs to be turned into a proper
function. All of this nicely reduces includes from intel_bw.h.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/743ba67e4e3c5dac4f5e58ab4d2357edea601d09.1750847509.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 1f86f3cb9cae1e6dbac77291ea5f103fc9e2d703..5942a3bae32c34884a506648d5f4db2d7a0e803c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -21,6 +21,41 @@
 #include "intel_uncore.h"
 #include "skl_watermark.h"
 
+struct intel_dbuf_bw {
+       unsigned int max_bw[I915_MAX_DBUF_SLICES];
+       u8 active_planes[I915_MAX_DBUF_SLICES];
+};
+
+struct intel_bw_state {
+       struct intel_global_state base;
+       struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
+
+       /*
+        * Contains a bit mask, used to determine, whether correspondent
+        * pipe allows SAGV or not.
+        */
+       u8 pipe_sagv_reject;
+
+       /* bitmask of active pipes */
+       u8 active_pipes;
+
+       /*
+        * From MTL onwards, to lock a QGV point, punit expects the peak BW of
+        * the selected QGV point as the parameter in multiples of 100MB/s
+        */
+       u16 qgv_point_peakbw;
+
+       /*
+        * Current QGV points mask, which restricts
+        * some particular SAGV states, not to confuse
+        * with pipe_sagv_mask.
+        */
+       u16 qgv_points_mask;
+
+       unsigned int data_rate[I915_MAX_PIPES];
+       u8 num_active_planes[I915_MAX_PIPES];
+};
+
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
        u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
@@ -872,6 +907,11 @@ static unsigned int intel_bw_data_rate(struct intel_display *display,
        return data_rate;
 }
 
+struct intel_bw_state *to_intel_bw_state(struct intel_global_state *obj_state)
+{
+       return container_of(obj_state, struct intel_bw_state, base);
+}
+
 struct intel_bw_state *
 intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
 {

diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 7728dc86a31a3cba7f99c16dfb92d83ca4a9bd47..d51f50c9d30219248e5799851e3d32a41e177bd2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -8,52 +8,14 @@
 
 #include <drm/drm_atomic.h>
 
-#include "intel_display_limits.h"
-#include "intel_display_power.h"
-#include "intel_global_state.h"
-
 struct intel_atomic_state;
+struct intel_bw_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
+struct intel_global_state;
 
-struct intel_dbuf_bw {
-       unsigned int max_bw[I915_MAX_DBUF_SLICES];
-       u8 active_planes[I915_MAX_DBUF_SLICES];
-};
-
-struct intel_bw_state {
-       struct intel_global_state base;
-       struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
-
-       /*
-        * Contains a bit mask, used to determine, whether correspondent
-        * pipe allows SAGV or not.
-        */
-       u8 pipe_sagv_reject;
-
-       /* bitmask of active pipes */
-       u8 active_pipes;
-
-       /*
-        * From MTL onwards, to lock a QGV point, punit expects the peak BW of
-        * the selected QGV point as the parameter in multiples of 100MB/s
-        */
-       u16 qgv_point_peakbw;
-
-       /*
-        * Current QGV points mask, which restricts
-        * some particular SAGV states, not to confuse
-        * with pipe_sagv_mask.
-        */
-       u16 qgv_points_mask;
-
-       unsigned int data_rate[I915_MAX_PIPES];
-       u8 num_active_planes[I915_MAX_PIPES];
-};
-
-#define to_intel_bw_state(global_state) \
-       container_of_const((global_state), struct intel_bw_state, base)
+struct intel_bw_state *to_intel_bw_state(struct intel_global_state *obj_state);
 
 struct intel_bw_state *
 intel_atomic_get_old_bw_state(struct intel_atomic_state *state);