clk: renesas: r8a7799[05]: Add MLP clocks

Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.

Similar to other R-Car Gen3 SoC, exact information on the parents of MLP
clocks on E3 and D3 is not available.  However, since the parents of
these clocks are not anyhow software-controllable, the only harm from
this is inexact information exported via debugfs.  So just keep the
parent set in the same way as with other Gen3 SoCs.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index faf60f7adc8d2c12d84f0a3ae4fc3823f63f4f61..d34d97baab35f3be58d44a7342ed20bad7207bd9 100644 (file)
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -200,6 +200,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
        DEF_MOD("du0",                   724,   R8A77990_CLK_S1D1),
        DEF_MOD("lvds",                  727,   R8A77990_CLK_S2D1),
 
+       DEF_MOD("mlp",                   802,   R8A77990_CLK_S2D1),
        DEF_MOD("vin5",                  806,   R8A77990_CLK_S1D2),
        DEF_MOD("vin4",                  807,   R8A77990_CLK_S1D2),
        DEF_MOD("etheravb",              812,   R8A77990_CLK_S3D2),

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 7713cfd99c1dac6cb3965aba78ff0b7d809af05b..525eef197fd9a9ab2c0118cab2f6357b15fa4b88 100644 (file)
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -160,6 +160,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
        DEF_MOD("du1",                   723,   R8A77995_CLK_S1D1),
        DEF_MOD("du0",                   724,   R8A77995_CLK_S1D1),
        DEF_MOD("lvds",                  727,   R8A77995_CLK_S2D1),
+       DEF_MOD("mlp",                   802,   R8A77995_CLK_S2D1),
        DEF_MOD("vin4",                  807,   R8A77995_CLK_S1D2),
        DEF_MOD("etheravb",              812,   R8A77995_CLK_S3D2),
        DEF_MOD("imr0",                  823,   R8A77995_CLK_S1D2),