arm64: dts: sprd: sc9860: Simplify clock nodes

The various "syscon" nodes in SC9860 are only referenced by clock
provider nodes in a 1:1 relationship, and nothing else references the
"syscon" nodes. There's no apparent reason for this split. The 2 nodes
can simply be merged into 1 node. The clock driver has supported using
either "reg" or "sprd,syscon" to access registers from the start, so
there shouldn't be any compatibility issues.

With this, DT schema warnings for missing a specific compatible with
"syscon" and non-MMIO devices on "simple-bus" are fixed.

Reviewed-by: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251124210031.767382-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
index d2456d633c39cd3a24155e49cd2361f4b2cfcdac..864ef0a17425c3e07178c68aa48c2a17aadc553a 100644 (file)
--- a/arch/arm64/boot/dts/sprd/sc9860.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
@@ -184,20 +184,6 @@
                                                | IRQ_TYPE_LEVEL_HIGH)>;
                };
 
-               pmu_gate: pmu-gate {
-                       compatible = "sprd,sc9860-pmu-gate";
-                       sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
-                       clocks = <&ext_26m>;
-                       #clock-cells = <1>;
-               };
-
-               pll: pll {
-                       compatible = "sprd,sc9860-pll";
-                       sprd,syscon = <&ana_regs>; /* 0x40400000 */
-                       clocks = <&pmu_gate 0>;
-                       #clock-cells = <1>;
-               };
-
                ap_clk: clock-controller@20000000 {
                        compatible = "sprd,sc9860-ap-clk";
                        reg = <0 0x20000000 0 0x400>;
@@ -214,19 +200,6 @@
                        #clock-cells = <1>;
                };
 
-               apahb_gate: apahb-gate {
-                       compatible = "sprd,sc9860-apahb-gate";
-                       sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
-                       clocks = <&aon_prediv 0>;
-                       #clock-cells = <1>;
-               };
-
-               aon_gate: aon-gate {
-                       compatible = "sprd,sc9860-aon-gate";
-                       sprd,syscon = <&aon_regs>; /* 0x402e0000 */
-                       clocks = <&aon_prediv 0>;
-                       #clock-cells = <1>;
-               };
 
                aonsecure_clk: clock-controller@40880000 {
                        compatible = "sprd,sc9860-aonsecure-clk";
@@ -235,13 +208,6 @@
                        #clock-cells = <1>;
                };
 
-               agcp_gate: agcp-gate {
-                       compatible = "sprd,sc9860-agcp-gate";
-                       sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
-                       clocks = <&aon_prediv 0>;
-                       #clock-cells = <1>;
-               };
-
                gpu_clk: clock-controller@60200000 {
                        compatible = "sprd,sc9860-gpu-clk";
                        reg = <0 0x60200000 0 0x400>;
@@ -256,13 +222,6 @@
                        #clock-cells = <1>;
                };
 
-               vsp_gate: vsp-gate {
-                       compatible = "sprd,sc9860-vsp-gate";
-                       sprd,syscon = <&vsp_regs>; /* 0x61100000 */
-                       clocks = <&vsp_clk 0>;
-                       #clock-cells = <1>;
-               };
-
                cam_clk: clock-controller@62000000 {
                        compatible = "sprd,sc9860-cam-clk";
                        reg = <0 0x62000000 0 0x4000>;
@@ -270,13 +229,6 @@
                        #clock-cells = <1>;
                };
 
-               cam_gate: cam-gate {
-                       compatible = "sprd,sc9860-cam-gate";
-                       sprd,syscon = <&cam_regs>; /* 0x62100000 */
-                       clocks = <&cam_clk 0>;
-                       #clock-cells = <1>;
-               };
-
                disp_clk: clock-controller@63000000 {
                        compatible = "sprd,sc9860-disp-clk";
                        reg = <0 0x63000000 0 0x400>;
@@ -284,20 +236,6 @@
                        #clock-cells = <1>;
                };
 
-               disp_gate: disp-gate {
-                       compatible = "sprd,sc9860-disp-gate";
-                       sprd,syscon = <&disp_regs>; /* 0x63100000 */
-                       clocks = <&disp_clk 0>;
-                       #clock-cells = <1>;
-               };
-
-               apapb_gate: apapb-gate {
-                       compatible = "sprd,sc9860-apapb-gate";
-                       sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
-                       clocks = <&ap_clk 0>;
-                       #clock-cells = <1>;
-               };
-
                funnel@10001000 { /* SoC Funnel */
                        compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
                        reg = <0 0x10001000 0 0x1000>;

diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
index a551e14ce8261fe7c6743e6b2aac0dd49d3c4597..2ecaa56001b8087ea0c0f48fb06b136930301dde 100644 (file)
--- a/arch/arm64/boot/dts/sprd/whale2.dtsi
+++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
@@ -18,49 +18,67 @@
                #size-cells = <2>;
                ranges;
 
-               ap_ahb_regs: syscon@20210000 {
-                       compatible = "syscon";
+               apahb_gate: clock-controller@20210000 {
                        reg = <0 0x20210000 0 0x10000>;
+                       compatible = "sprd,sc9860-apahb-gate";
+                       clocks = <&aon_prediv 0>;
+                       #clock-cells = <1>;
                };
 
-               pmu_regs: syscon@402b0000 {
-                       compatible = "syscon";
+               pmu_gate: clock-controller@402b0000 {
                        reg = <0 0x402b0000 0 0x10000>;
+                       compatible = "sprd,sc9860-pmu-gate";
+                       clocks = <&ext_26m>;
+                       #clock-cells = <1>;
                };
 
-               aon_regs: syscon@402e0000 {
-                       compatible = "syscon";
+               aon_gate: clock-controller@402e0000 {
                        reg = <0 0x402e0000 0 0x10000>;
+                       compatible = "sprd,sc9860-aon-gate";
+                       clocks = <&aon_prediv 0>;
+                       #clock-cells = <1>;
                };
 
-               ana_regs: syscon@40400000 {
-                       compatible = "syscon";
+               pll: clock-controller@40400000 {
                        reg = <0 0x40400000 0 0x10000>;
+                       compatible = "sprd,sc9860-pll";
+                       clocks = <&pmu_gate 0>;
+                       #clock-cells = <1>;
                };
 
-               agcp_regs: syscon@415e0000 {
-                       compatible = "syscon";
+               agcp_gate: clock-controller@415e0000 {
                        reg = <0 0x415e0000 0 0x1000000>;
+                       compatible = "sprd,sc9860-agcp-gate";
+                       clocks = <&aon_prediv 0>;
+                       #clock-cells = <1>;
                };
 
-               vsp_regs: syscon@61100000 {
-                       compatible = "syscon";
+               vsp_gate: clock-controller@61100000 {
                        reg = <0 0x61100000 0 0x10000>;
+                       compatible = "sprd,sc9860-vsp-gate";
+                       clocks = <&vsp_clk 0>;
+                       #clock-cells = <1>;
                };
 
-               cam_regs: syscon@62100000 {
-                       compatible = "syscon";
+               cam_gate: clock-controller@62100000 {
                        reg = <0 0x62100000 0 0x10000>;
+                       compatible = "sprd,sc9860-cam-gate";
+                       clocks = <&cam_clk 0>;
+                       #clock-cells = <1>;
                };
 
-               disp_regs: syscon@63100000 {
-                       compatible = "syscon";
+               disp_gate: clock-controller@63100000 {
                        reg = <0 0x63100000 0 0x10000>;
+                       compatible = "sprd,sc9860-disp-gate";
+                       clocks = <&disp_clk 0>;
+                       #clock-cells = <1>;
                };
 
-               ap_apb_regs: syscon@70b00000 {
-                       compatible = "syscon";
+               apapb_gate: clock-controller@70b00000 {
                        reg = <0 0x70b00000 0 0x40000>;
+                       compatible = "sprd,sc9860-apapb-gate";
+                       clocks = <&ap_clk 0>;
+                       #clock-cells = <1>;
                };
 
                ap-apb@70000000 {