]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
KVM: x86: Advertise support for AMD's PREFETCHI
authorBabu Moger <babu.moger@amd.com>
Tue, 8 Apr 2025 22:57:09 +0000 (17:57 -0500)
committerSean Christopherson <seanjc@google.com>
Thu, 24 Apr 2025 18:18:35 +0000 (11:18 -0700)
The latest AMD platform has introduced a new instruction called PREFETCHI.
This instruction loads a cache line from a specified memory address into
the indicated data or instruction cache level, based on locality reference
hints.

Feature bit definition:
CPUID_Fn80000021_EAX [bit 20] - Indicates support for IC prefetch.

This feature is analogous to Intel's PREFETCHITI (CPUID.(EAX=7,ECX=1):EDX),
though the CPUID bit definitions differ between AMD and Intel.

Advertise support to userspace, as no additional enabling is necessary
(PREFETCHI can't be intercepted as there's no instruction specific behavior
that needs to be virtualize).

The feature is documented in Processor Programming Reference (PPR)
for AMD Family 1Ah Model 02h, Revision C1 (Link below).

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/ee1c08fc400bb574a2b8f2c6a0bd9def10a29d35.1744130533.git.babu.moger@amd.com
[sean: rewrite shortlog to highlight the KVM functionality]
Signed-off-by: Sean Christopherson <seanjc@google.com>
arch/x86/include/asm/cpufeatures.h
arch/x86/kvm/cpuid.c

index 97af896de2cebfd248d5a5eb38479af8f54dedcc..389d8a6b96bbdc8570857fe7dcc801384f4e7317 100644 (file)
 #define X86_FEATURE_AUTOIBRS           (20*32+ 8) /* Automatic IBRS */
 #define X86_FEATURE_NO_SMM_CTL_MSR     (20*32+ 9) /* SMM_CTL MSR is not present */
 
+#define X86_FEATURE_PREFETCHI          (20*32+20) /* Prefetch Data/Instruction to Cache Level */
 #define X86_FEATURE_SBPB               (20*32+27) /* Selective Branch Prediction Barrier */
 #define X86_FEATURE_IBPB_BRTYPE                (20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
 #define X86_FEATURE_SRSO_NO            (20*32+29) /* CPU is not affected by SRSO */
index 5d4de19b7c221b1b5d526fa401c4286897632417..41df8729c167dc4f3554e8be289f615f564d5011 100644 (file)
@@ -1168,6 +1168,7 @@ void kvm_set_cpu_caps(void)
                F(NULL_SEL_CLR_BASE),
                /* UpperAddressIgnore */
                F(AUTOIBRS),
+               F(PREFETCHI),
                EMULATED_F(NO_SMM_CTL_MSR),
                /* PrefetchCtlMsr */
                /* GpOnUserCpuid */