]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
gpio: qcom: move pm8550 gpio to new driver
authorNeil Armstrong <neil.armstrong@linaro.org>
Mon, 30 Jun 2025 16:04:45 +0000 (18:04 +0200)
committerCasey Connolly <casey.connolly@linaro.org>
Mon, 14 Jul 2025 13:35:24 +0000 (15:35 +0200)
Move support of the pm8550 gpios to the newly introduced
driver and drop the compatible entry and the read-only quirk
at the same time from the old driver.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250630-topic-sm8x50-pmic-gpio-pinctrl-new-v2-2-cc1512931197@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
drivers/gpio/qcom_pmic_gpio.c
drivers/gpio/qcom_spmi_gpio.c

index cd9f3926ac41d84161b1e5311d9a99bb0b4a68ff..4458c55cd3da4d279b360b701348b50247036198 100644 (file)
 #define REG_EN_CTL             0x46
 #define REG_EN_CTL_ENABLE      (1 << 7)
 
-/**
- * pmic_gpio_match_data - platform specific configuration
- *
- * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them.
- * This is a workaround for an unknown bug on some platforms where trying to write the
- * GPIO configuration registers causes the board to hang.
- */
-enum pmic_gpio_quirks {
-       QCOM_PMIC_QUIRK_READONLY = (1 << 0),
-};
-
 struct qcom_pmic_gpio_data {
        uint32_t pid; /* Peripheral ID on SPMI bus */
        bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
@@ -128,13 +117,8 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
 {
        struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
        uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
-       ulong quirks = dev_get_driver_data(dev);
        int ret = 0;
 
-       /* Some PMICs don't like their GPIOs being configured */
-       if (quirks & QCOM_PMIC_QUIRK_READONLY)
-               return 0;
-
        /* Disable the GPIO */
        ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
                              REG_EN_CTL_ENABLE, 0);
@@ -278,7 +262,6 @@ static int qcom_gpio_bind(struct udevice *dev)
 {
 
        struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
-       ulong quirks = dev_get_driver_data(dev);
        struct udevice *child;
        struct driver *drv;
        int ret;
@@ -292,7 +275,7 @@ static int qcom_gpio_bind(struct udevice *dev)
        /* Bind the GPIO driver as a child of the PMIC. */
        ret = device_bind_with_driver_data(dev, drv,
                                           dev->name,
-                                          quirks, dev_ofnode(dev), &child);
+                                          0, dev_ofnode(dev), &child);
        if (ret)
                return log_msg_ret("bind", ret);
 
@@ -365,7 +348,6 @@ static const struct udevice_id qcom_gpio_ids[] = {
        { .compatible = "qcom,pms405-gpio" },
        { .compatible = "qcom,pm6125-gpio" },
        { .compatible = "qcom,pm8150-gpio" },
-       { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
        { }
 };
 
index 2bb0f0d10c32ff55d3fd5c61b9bc2999878bfea6..22c8072534e9188445f0aaef5336863fd1da7a75 100644 (file)
@@ -743,6 +743,7 @@ static int qcom_spmi_pmic_gpio_probe(struct udevice *dev)
 }
 
 static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = {
+       { .compatible = "qcom,pm8550-gpio" },
        { .compatible = "qcom,pm8550b-gpio" },
        { .compatible = "qcom,pm8550ve-gpio" },
        { .compatible = "qcom,pm8550vs-gpio" },