ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30

The DRAM refresh-interval is getting erroneously set to "1" on exiting
from memory self-refreshing mode. The clobbered interval causes the
"refresh request overflow timeout" error raised by the External Memory
Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20,
but EMC registers are not latched after exiting from self-refreshing mode
on Tegra20 and hence refresh-interval is not altered until an event that
causes registers latching happens.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 5c8e638ee51a3b590cc8274a3edb22e5a93dd996..dedeebfccc55b45ba2b8d03d88aa5dd6d400263a 100644 (file)
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -32,7 +32,6 @@
 
 #define EMC_CFG                                0xc
 #define EMC_ADR_CFG                    0x10
-#define EMC_REFRESH                    0x70
 #define EMC_NOP                                0xdc
 #define EMC_SELF_REF                   0xe0
 #define EMC_REQ_CTRL                   0x2b0
@@ -397,7 +396,6 @@ padload_done:
        mov     r1, #1
        str     r1, [r0, #EMC_NOP]
        str     r1, [r0, #EMC_NOP]
-       str     r1, [r0, #EMC_REFRESH]
 
        emc_device_mask r1, r0
 

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index efc6493b61f3ad9b275b927dc04c55aab078b4cf..7727e005c30e38fa1938569dd884b32316392984 100644 (file)
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -29,7 +29,6 @@
 #define EMC_CFG                                0xc
 #define EMC_ADR_CFG                    0x10
 #define EMC_TIMING_CONTROL             0x28
-#define EMC_REFRESH                    0x70
 #define EMC_NOP                                0xdc
 #define EMC_SELF_REF                   0xe0
 #define EMC_MRW                                0xe8
@@ -459,7 +458,6 @@ emc_wait_auto_cal_onetime:
        cmp     r10, #TEGRA30
        streq   r1, [r0, #EMC_NOP]
        streq   r1, [r0, #EMC_NOP]
-       streq   r1, [r0, #EMC_REFRESH]
 
        emc_device_mask r1, r0