(define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3"
(cond [(match_test "TARGET_V850")
- (const_string "v850")
- (match_test "TARGET_V850E")
- (const_string "v850e")
- (match_test "TARGET_V850E1")
- (const_string "v850e1")
- (match_test "TARGET_V850E2")
- (const_string "v850e2")
- (match_test "TARGET_V850E2")
- (const_string "v850e2v3")]
- (const_string "none")))
+ (const_string "v850")
+ (match_test "TARGET_V850E")
+ (const_string "v850e")
+ (match_test "TARGET_V850E1")
+ (const_string "v850e1")
+ (match_test "TARGET_V850E2")
+ (const_string "v850e2")
+ (match_test "TARGET_V850E2")
+ (const_string "v850e2v3")]
+ (const_string "none")))
;; Condition code settings.
;; none - insn does not affect cc
"st.w %2,%1[%0]"
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")])
+
;; movqi
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
- "
-{
- /* One of the ops has to be in a register or 0 */
- if (!register_operand (operand0, QImode)
- && !reg_or_0_operand (operand1, QImode))
- operands[1] = copy_to_mode_reg (QImode, operand1);
-}")
+ {
+ /* One of the ops has to be in a register or 0 */
+ if (!register_operand (operand0, QImode)
+ && !reg_or_0_operand (operand1, QImode))
+ operands[1] = copy_to_mode_reg (QImode, operand1);
+ })
(define_insn "*movqi_internal"
[(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
(match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
"register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode)"
- "* return output_move_single (operands);"
+{
+ return output_move_single (operands);
+}
[(set_attr "length" "2,4,2,2,4,4,4")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,load,other,load,store,store")])
[(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
- "
{
/* One of the ops has to be in a register or 0 */
if (!register_operand (operand0, HImode)
&& !reg_or_0_operand (operand1, HImode))
operands[1] = copy_to_mode_reg (HImode, operand1);
-}")
+})
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
(match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
"register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode)"
- "* return output_move_single (operands);"
+{
+ return output_move_single (operands);
+}
[(set_attr "length" "2,4,2,2,4,4,4")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,load,other,load,store,store")])
[(set (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))]
""
- "
-{
- /* One of the ops has to be in a register or 0 */
- if (!register_operand (operand0, SImode)
- && !reg_or_0_operand (operand1, SImode))
- operands[1] = copy_to_mode_reg (SImode, operand1);
-
- /* Some constants, as well as symbolic operands
- must be done with HIGH & LO_SUM patterns. */
- if (CONSTANT_P (operands[1])
- && GET_CODE (operands[1]) != HIGH
- && ! (TARGET_V850E || TARGET_V850E2_ALL)
- && !special_symbolref_operand (operands[1], VOIDmode)
- && !(GET_CODE (operands[1]) == CONST_INT
- && (CONST_OK_FOR_J (INTVAL (operands[1]))
- || CONST_OK_FOR_K (INTVAL (operands[1]))
- || CONST_OK_FOR_L (INTVAL (operands[1])))))
- {
- rtx temp;
-
- if (reload_in_progress || reload_completed)
- temp = operands[0];
- else
- temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_rtx_SET (SImode, temp,
- gen_rtx_HIGH (SImode, operand1)));
- emit_insn (gen_rtx_SET (SImode, operand0,
- gen_rtx_LO_SUM (SImode, temp, operand1)));
- DONE;
- }
-}")
+ {
+ /* One of the ops has to be in a register or 0 */
+ if (!register_operand (operand0, SImode)
+ && !reg_or_0_operand (operand1, SImode))
+ operands[1] = copy_to_mode_reg (SImode, operand1);
+
+ /* Some constants, as well as symbolic operands
+ must be done with HIGH & LO_SUM patterns. */
+ if (CONSTANT_P (operands[1])
+ && GET_CODE (operands[1]) != HIGH
+ && ! (TARGET_V850E || TARGET_V850E2_ALL)
+ && !special_symbolref_operand (operands[1], VOIDmode)
+ && !(GET_CODE (operands[1]) == CONST_INT
+ && (CONST_OK_FOR_J (INTVAL (operands[1]))
+ || CONST_OK_FOR_K (INTVAL (operands[1]))
+ || CONST_OK_FOR_L (INTVAL (operands[1])))))
+ {
+ rtx temp;
+
+ if (reload_in_progress || reload_completed)
+ temp = operands[0];
+ else
+ temp = gen_reg_rtx (SImode);
+
+ emit_insn (gen_rtx_SET (SImode, temp,
+ gen_rtx_HIGH (SImode, operand1)));
+ emit_insn (gen_rtx_SET (SImode, operand0,
+ gen_rtx_LO_SUM (SImode, temp, operand1)));
+ DONE;
+ }
+ })
;; This is the same as the following pattern, except that it includes
;; support for arbitrary 32-bit immediates.
"(TARGET_V850E || TARGET_V850E2_ALL)
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
- "* return output_move_single (operands);"
+{
+ return output_move_single (operands);
+}
[(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,load,other,load,other,store,store,other")])
(match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
"register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode)"
- "* return output_move_single (operands);"
+{
+ return output_move_single (operands);
+}
[(set_attr "length" "2,4,4,2,2,4,4,4,4")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,load,other,load,store,store,other")])
(match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
"register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode)"
- "* return output_move_single (operands);"
+{
+ return output_move_single (operands);
+}
[(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,other,load,other,load,store,store,other")])
(compare (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
""
- "
-{
- v850_compare_op0 = operands[0];
- v850_compare_op1 = operands[1];
- DONE;
-}")
+ {
+ v850_compare_op0 = operands[0];
+ v850_compare_op1 = operands[1];
+ DONE;
+ })
(define_insn "cmpsi_insn"
[(set (cc0)
(compare (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "register_operand" "r")))]
"TARGET_V850E2V3"
- "
-{
- v850_compare_op0 = operands[0];
- v850_compare_op1 = operands[1];
- DONE;
-}")
+ {
+ v850_compare_op0 = operands[0];
+ v850_compare_op1 = operands[1];
+ DONE;
+ })
(define_expand "cmpdf"
[(set (reg:CC CC_REGNUM)
(compare (match_operand:DF 0 "even_reg_operand" "r")
(match_operand:DF 1 "even_reg_operand" "r")))]
"TARGET_V850E2V3"
- "
-{
- v850_compare_op0 = operands[0];
- v850_compare_op1 = operands[1];
- DONE;
-}")
+ {
+ v850_compare_op0 = operands[0];
+ v850_compare_op1 = operands[1];
+ DONE;
+ })
;; ----------------------------------------------------------------------
;; ADD INSTRUCTIONS
(sign_extend:SI (match_operand:HI 1 "register_operand" ""))
(sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
""
- "if (GET_CODE (operands[2]) == CONST_INT)
- {
- emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
- DONE;
- }")
+ {
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ })
(define_insn "*mulhisi3_internal1"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_dup 2)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_V850E || TARGET_V850E2_ALL"
- {
- if (TARGET_V850E2_ALL)
- return "divq %2,%0,%3";
+{
+ if (TARGET_V850E2_ALL)
+ return "divq %2,%0,%3";
else
- return "div %2,%0,%3";
- }
+ return "div %2,%0,%3";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "div")])
(match_dup 2)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_V850E || TARGET_V850E2_ALL"
- {
- if (TARGET_V850E2_ALL)
- return "divqu %2,%0,%3";
- else
- return "divu %2,%0,%3";
- }
+{
+ if (TARGET_V850E2_ALL)
+ return "divqu %2,%0,%3";
+ else
+ return "divu %2,%0,%3";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "div")])
(match_operand:QI 1 "not_power_of_two_operand" "")) 0))
(clobber (reg:CC CC_REGNUM))]
""
- "*
{
rtx xoperands[2];
xoperands[0] = operands[0];
xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
- output_asm_insn (\"clr1 %M1,%0\", xoperands);
- return \"\";
-}"
+ output_asm_insn ("clr1 %M1,%0", xoperands);
+ return "";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(match_operand:HI 1 "not_power_of_two_operand" "")) 0))
(clobber (reg:CC CC_REGNUM))]
""
- "*
{
int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
xoperands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), log2 / 8));
xoperands[1] = GEN_INT (log2 % 8);
- output_asm_insn (\"clr1 %1,%0\", xoperands);
- return \"\";
-}"
+ output_asm_insn ("clr1 %1,%0", xoperands);
+ return "";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(match_operand:SI 1 "not_power_of_two_operand" "")))
(clobber (reg:CC CC_REGNUM))]
""
- "*
{
int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
xoperands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), log2 / 8));
xoperands[1] = GEN_INT (log2 % 8);
- output_asm_insn (\"clr1 %1,%0\", xoperands);
- return \"\";
-}"
+ output_asm_insn ("clr1 %1,%0", xoperands);
+ return "";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
(match_operand 1 "power_of_two_operand" "")) 0))]
""
- "*
{
int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8)
- return \"set1 %M1,%0\";
+ return "set1 %M1,%0";
else
{
rtx xoperands[2];
plus_constant (XEXP (operands[0], 0),
log2 / 8));
xoperands[1] = GEN_INT (log2 % 8);
- output_asm_insn (\"set1 %1,%0\", xoperands);
+ output_asm_insn ("set1 %1,%0", xoperands);
}
- return \"\";
-}"
+ return "";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(match_operand 1 "power_of_two_operand" "")))
(clobber (reg:CC CC_REGNUM))]
""
- "*
{
int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8)
- return \"set1 %M1,%0\";
+ return "set1 %M1,%0";
else
{
rtx xoperands[2];
plus_constant (XEXP (operands[0], 0),
log2 / 8));
xoperands[1] = GEN_INT (log2 % 8);
- output_asm_insn (\"set1 %1,%0\", xoperands);
+ output_asm_insn ("set1 %1,%0", xoperands);
}
- return \"\";
-}"
+ return "";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
(match_operand 1 "power_of_two_operand" "")) 0))]
""
- "*
{
int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8)
- return \"not1 %M1,%0\";
+ return "not1 %M1,%0";
else
{
rtx xoperands[2];
plus_constant (XEXP (operands[0], 0),
log2 / 8));
xoperands[1] = GEN_INT (log2 % 8);
- output_asm_insn (\"not1 %1,%0\", xoperands);
+ output_asm_insn ("not1 %1,%0", xoperands);
}
- return \"\";
-}"
+ return "";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(match_operand 1 "power_of_two_operand" "")))
(clobber (reg:CC CC_REGNUM))]
""
- "*
{
int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8)
- return \"not1 %M1,%0\";
+ return "not1 %M1,%0";
else
{
rtx xoperands[2];
plus_constant (XEXP (operands[0], 0),
log2 / 8));
xoperands[1] = GEN_INT (log2 % 8);
- output_asm_insn (\"not1 %1,%0\", xoperands);
+ output_asm_insn ("not1 %1,%0", xoperands);
}
- return \"\";
-}"
+ return "";
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(match_operator:SI 1 "comparison_operator"
[(cc0) (const_int 0)]))]
""
- "*
{
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT
|| GET_CODE (operands[1]) == LT))
return 0;
- return \"setf %c1,%0\";
-}"
+ return "setf %c1,%0";
+}
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")])
(match_operand:SI 2 "reg_or_const_operand" "rJ")
(match_operand:SI 3 "reg_or_const_operand" "rI")))]
"(TARGET_V850E || TARGET_V850E2_ALL)"
- "
-{
- if ( (GET_CODE (operands[2]) == CONST_INT
- && GET_CODE (operands[3]) == CONST_INT))
- {
- int o2 = INTVAL (operands[2]);
- int o3 = INTVAL (operands[3]);
-
- if (o2 == 1 && o3 == 0)
- FAIL; /* setf */
- if (o3 == 1 && o2 == 0)
- FAIL; /* setf */
- if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0)
- FAIL; /* setf + shift */
- if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0)
- FAIL; /* setf + shift */
- if (o2 != 0)
- operands[2] = copy_to_mode_reg (SImode, operands[2]);
- if (o3 !=0 )
- operands[3] = copy_to_mode_reg (SImode, operands[3]);
- }
- else
- {
- if (GET_CODE (operands[2]) != REG)
- operands[2] = copy_to_mode_reg (SImode,operands[2]);
- if (GET_CODE (operands[3]) != REG)
- operands[3] = copy_to_mode_reg (SImode, operands[3]);
- }
-}")
+ {
+ if ((GET_CODE (operands[2]) == CONST_INT
+ && GET_CODE (operands[3]) == CONST_INT))
+ {
+ int o2 = INTVAL (operands[2]);
+ int o3 = INTVAL (operands[3]);
+
+ if (o2 == 1 && o3 == 0)
+ FAIL; /* setf */
+ if (o3 == 1 && o2 == 0)
+ FAIL; /* setf */
+ if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0)
+ FAIL; /* setf + shift */
+ if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0)
+ FAIL; /* setf + shift */
+ if (o2 != 0)
+ operands[2] = copy_to_mode_reg (SImode, operands[2]);
+ if (o3 !=0 )
+ operands[3] = copy_to_mode_reg (SImode, operands[3]);
+ }
+ else
+ {
+ if (GET_CODE (operands[2]) != REG)
+ operands[2] = copy_to_mode_reg (SImode,operands[2]);
+ if (GET_CODE (operands[3]) != REG)
+ operands[3] = copy_to_mode_reg (SImode, operands[3]);
+ }
+ })
;; ??? Clobbering the condition codes is overkill.
(ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
(ashift:SI (match_dup 0) (const_int 1))))
(clobber (reg:CC CC_REGNUM))])]
- "
-{
- operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
- if (INTVAL (operands[2]) & 0x1)
- operands[7] = operands[1];
- else
- operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
- GET_MODE (operands[1]),
- XEXP (operands[1], 0), XEXP (operands[1], 1));
-}")
+ {
+ operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
+ if (INTVAL (operands[2]) & 0x1)
+ operands[7] = operands[1];
+ else
+ operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
+ GET_MODE (operands[1]),
+ XEXP (operands[1], 0), XEXP (operands[1], 1));
+ })
;; ---------------------------------------------------------------------
;; BYTE SWAP INSTRUCTIONS
(match_operand:HI 2 "const_int_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
"(TARGET_V850E || TARGET_V850E2_ALL)"
- "
-{
- if (INTVAL (operands[2]) != 8)
- FAIL;
-}")
+ {
+ if (INTVAL (operands[2]) != 8)
+ FAIL;
+ })
(define_insn "*rotlhi3_8"
[(set (match_operand:HI 0 "register_operand" "=r")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
"(TARGET_V850E || TARGET_V850E2_ALL)"
- "
-{
- if (INTVAL (operands[2]) != 16)
- FAIL;
-}")
+ {
+ if (INTVAL (operands[2]) != 16)
+ FAIL;
+ })
(define_insn "*rotlsi3_16"
[(set (match_operand:SI 0 "register_operand" "=r")
(label_ref (match_operand 0 "" ""))
(pc)))]
""
- "*
{
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT
return 0;
if (get_attr_length (insn) == 2)
- return \"b%b1 %l0\";
+ return "b%b1 %l0";
else
- return \"b%B1 .+6 ; jr %l0\";
-}"
+ return "b%B1 .+6 ; jr %l0";
+}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(pc)
(label_ref (match_operand 0 "" ""))))]
""
- "*
{
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT
|| GET_CODE (operands[1]) == LT))
return 0;
if (get_attr_length (insn) == 2)
- return \"b%B1 %l0\";
+ return "b%B1 %l0";
else
- return \"b%b1 .+6 ; jr %l0\";
-}"
+ return "b%b1 .+6 ; jr %l0";
+}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_V850E2V3"
- "*
{
if (get_attr_length (insn) == 2)
- return \"bz %l0\";
+ return "bz %l0";
else
- return \"bnz 1f ; jr %l0 ; 1:\";
-}"
+ return "bnz 1f ; jr %l0 ; 1:";
+}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_V850E2V3"
- "*
{
if (get_attr_length (insn) == 2)
- return \"bnz %l0\";
+ return "bnz %l0";
else
- return \"bz 1f ; jr %l0 ; 1:\";
-}"
+ return "bz 1f ; jr %l0 ; 1:";
+}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_V850E2V3"
- "*
{
if (get_attr_length (insn) == 2)
- return \"bnz %l0\";
+ return "bnz %l0";
else
- return \"bz 1f ; jr %l0 ; 1:\";
-}"
+ return "bz 1f ; jr %l0 ; 1:";
+}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_V850E2V3"
- "*
{
if (get_attr_length (insn) == 2)
- return \"bz %l0\";
+ return "bz %l0";
else
- return \"bnz 1f ; jr %l0 ; 1:\";
-}"
+ return "bnz 1f ; jr %l0 ; 1:";
+}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
[(set (pc)
(label_ref (match_operand 0 "" "")))]
""
- "*
{
if (get_attr_length (insn) == 2)
- return \"br %0\";
+ return "br %0";
else
- return \"jr %0\";
-}"
+ return "jr %0";
+}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(match_operand:SI 2 "register_operand" "")
(match_operand 3 "" "") (match_operand 4 "" "")]
""
- "
-{
- rtx reg = gen_reg_rtx (SImode);
- rtx tableaddress = gen_reg_rtx (SImode);
- rtx test;
- rtx mem;
-
- /* Subtract the lower bound from the index. */
- emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
-
- /* Compare the result against the number of table entries;
- branch to the default label if out of range of the table. */
- test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]);
- emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4]));
-
- /* Shift index for the table array access. */
- emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
- /* Load the table address into a pseudo. */
- emit_insn (gen_movsi (tableaddress,
- gen_rtx_LABEL_REF (Pmode, operands[3])));
- /* Add the table address to the index. */
- emit_insn (gen_addsi3 (reg, reg, tableaddress));
- /* Load the table entry. */
- mem = gen_const_mem (CASE_VECTOR_MODE, reg);
- if (! TARGET_BIG_SWITCH)
- {
- rtx reg2 = gen_reg_rtx (HImode);
- emit_insn (gen_movhi (reg2, mem));
- emit_insn (gen_extendhisi2 (reg, reg2));
- }
- else
- emit_insn (gen_movsi (reg, mem));
- /* Add the table address. */
- emit_insn (gen_addsi3 (reg, reg, tableaddress));
- /* Branch to the switch label. */
- emit_jump_insn (gen_tablejump (reg, operands[3]));
- DONE;
-}")
+ {
+ rtx reg = gen_reg_rtx (SImode);
+ rtx tableaddress = gen_reg_rtx (SImode);
+ rtx test;
+ rtx mem;
+
+ /* Subtract the lower bound from the index. */
+ emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
+
+ /* Compare the result against the number of table entries;
+ branch to the default label if out of range of the table. */
+ test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]);
+ emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4]));
+
+ /* Shift index for the table array access. */
+ emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
+ /* Load the table address into a pseudo. */
+ emit_insn (gen_movsi (tableaddress,
+ gen_rtx_LABEL_REF (Pmode, operands[3])));
+ /* Add the table address to the index. */
+ emit_insn (gen_addsi3 (reg, reg, tableaddress));
+ /* Load the table entry. */
+ mem = gen_const_mem (CASE_VECTOR_MODE, reg);
+ if (! TARGET_BIG_SWITCH)
+ {
+ rtx reg2 = gen_reg_rtx (HImode);
+ emit_insn (gen_movhi (reg2, mem));
+ emit_insn (gen_extendhisi2 (reg, reg2));
+ }
+ else
+ emit_insn (gen_movsi (reg, mem));
+ /* Add the table address. */
+ emit_insn (gen_addsi3 (reg, reg, tableaddress));
+ /* Branch to the switch label. */
+ emit_jump_insn (gen_tablejump (reg, operands[3]));
+ DONE;
+ })
;; Call subroutine with no return value.
[(call (match_operand:QI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))]
""
- "
-{
- if (! call_address_operand (XEXP (operands[0], 0), QImode)
- || TARGET_LONG_CALLS)
- XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
- if (TARGET_LONG_CALLS)
- emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
- else
- emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
+ {
+ if (! call_address_operand (XEXP (operands[0], 0), QImode)
+ || TARGET_LONG_CALLS)
+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
+ if (TARGET_LONG_CALLS)
+ emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
+ else
+ emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
- DONE;
-}")
+ DONE;
+ })
(define_insn "call_internal_short"
[(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
(match_operand:SI 1 "general_operand" "g,g"))
(clobber (reg:SI 31))]
"TARGET_LONG_CALLS"
- "*
- {
+{
if (which_alternative == 0)
{
if (GET_CODE (operands[0]) == REG)
- return \"jarl %0,r31\";
+ return "jarl %0,r31";
else
- return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\";
+ return "movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11";
}
else
- return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\";
- }"
+ return "jarl .+4,r31 ; add 4,r31 ; jmp %0";
+}
[(set_attr "length" "16,8")
(set_attr "cc" "clobber,clobber")]
)
(call (match_operand:QI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
""
- "
-{
- if (! call_address_operand (XEXP (operands[1], 0), QImode)
- || TARGET_LONG_CALLS)
- XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
- if (TARGET_LONG_CALLS)
- emit_call_insn (gen_call_value_internal_long (operands[0],
- XEXP (operands[1], 0),
- operands[2]));
- else
- emit_call_insn (gen_call_value_internal_short (operands[0],
- XEXP (operands[1], 0),
- operands[2]));
- DONE;
-}")
+ {
+ if (! call_address_operand (XEXP (operands[1], 0), QImode)
+ || TARGET_LONG_CALLS)
+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
+ if (TARGET_LONG_CALLS)
+ emit_call_insn (gen_call_value_internal_long (operands[0],
+ XEXP (operands[1], 0),
+ operands[2]));
+ else
+ emit_call_insn (gen_call_value_internal_short (operands[0],
+ XEXP (operands[1], 0),
+ operands[2]));
+ DONE;
+ })
(define_insn "call_value_internal_short"
[(set (match_operand 0 "" "=r,r")
(match_operand:SI 2 "general_operand" "g,g")))
(clobber (reg:SI 31))]
"TARGET_LONG_CALLS"
- "*
- {
+{
if (which_alternative == 0)
{
if (GET_CODE (operands[1]) == REG)
- return \"jarl %1, r31\";
+ return "jarl %1, r31";
else
/* Reload can generate this pattern.... */
- return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\";
+ return "movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11";
}
else
- return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\";
- }"
+ return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
+}
[(set_attr "length" "16,8")
(set_attr "cc" "clobber,clobber")]
)
{
if (! (TARGET_V850E || TARGET_V850E2_ALL))
operands[1] = force_reg (HImode, operands[1]);
- }
-)
+ })
(define_insn "*zero_extendqisi2_v850e"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(define_insn "*zero_extendqisi2_v850"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI
- (match_operand:QI 1 "register_operand" "r")))
+ (match_operand:QI 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander
""
"andi 255,%1,%0"
{
if (! (TARGET_V850E || TARGET_V850E2_ALL))
operands[1] = force_reg (QImode, operands[1]);
- }
-)
+ })
;;- sign extension instructions
(const_int 16)))
(clobber (reg:CC CC_REGNUM))])]
""
- "
-{
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode);
-}")
+ {
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = gen_reg_rtx (SImode);
+ })
;; ??? The extendqisi2 pattern should not emit shifts for v850e?
(const_int 24)))
(clobber (reg:CC CC_REGNUM))])]
""
- "
-{
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode);
-}")
+ {
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = gen_reg_rtx (SImode);
+ })
\f
;; ----------------------------------------------------------------------
;; SHIFTS
(define_expand "prologue"
[(const_int 0)]
""
- "expand_prologue (); DONE;")
+ {
+ expand_prologue ();
+ DONE;
+ })
(define_expand "epilogue"
[(return)]
""
- "
-{
- expand_epilogue ();
- DONE;
-}")
+ {
+ expand_epilogue ();
+ DONE;
+ })
(define_insn "return_simple"
[(return)]
(match_operand:SI 2 "immediate_operand" "i")))
(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
"TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
- "* return construct_prepare_instruction (operands[0]);
- "
+{
+ return construct_prepare_instruction (operands[0]);
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
(match_operand:SI 2 "immediate_operand" "i")))
(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
"TARGET_PROLOG_FUNCTION"
- "* return construct_save_jarl (operands[0]);
- "
+{
+ return construct_save_jarl (operands[0]);
+}
[(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
(const_string "16")
(const_string "4")))
(mem:SI (plus:SI (reg:SI 3)
(match_operand:SI 3 "immediate_operand" "i"))))])]
"TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
- "* return construct_dispose_instruction (operands[0]);
- "
+{
+ return construct_dispose_instruction (operands[0]);
+}
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
(mem:SI (plus:SI (reg:SI 3)
(match_operand:SI 3 "immediate_operand" "i"))))])]
"TARGET_PROLOG_FUNCTION"
- "* return construct_restore_jr (operands[0]);
- "
+{
+ return construct_restore_jr (operands[0]);
+}
[(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
(const_string "12")
(const_string "4")))
;; without saving its previous value. So if the interrupt handler
;; or its caller could possibly execute the CALLT insn, save_interrupt
;; MUST NOT be called via CALLT.
- "*
{
- output_asm_insn (\"addi -28, sp, sp\", operands);
- output_asm_insn (\"st.w r1, 24[sp]\", operands);
- output_asm_insn (\"st.w r10, 12[sp]\", operands);
- output_asm_insn (\"st.w r11, 16[sp]\", operands);
- output_asm_insn (\"stsr ctpc, r10\", operands);
- output_asm_insn (\"st.w r10, 20[sp]\", operands);
- output_asm_insn (\"stsr ctpsw, r10\", operands);
- output_asm_insn (\"st.w r10, 24[sp]\", operands);
- output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands);
- return \"\";
-}"
+ output_asm_insn ("addi -28, sp, sp", operands);
+ output_asm_insn ("st.w r1, 24[sp]", operands);
+ output_asm_insn ("st.w r10, 12[sp]", operands);
+ output_asm_insn ("st.w r11, 16[sp]", operands);
+ output_asm_insn ("stsr ctpc, r10", operands);
+ output_asm_insn ("st.w r10, 20[sp]", operands);
+ output_asm_insn ("stsr ctpsw, r10", operands);
+ output_asm_insn ("st.w r10, 24[sp]", operands);
+ output_asm_insn ("callt ctoff(__callt_save_interrupt)", operands);
+ return "";
+}
[(set_attr "length" "26")
(set_attr "cc" "clobber")])
(set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10))
(set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))]
""
- "*
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
- return \"addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10\";
+ return "addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10";
else
{
- output_asm_insn (\"addi -20, sp, sp\", operands);
- output_asm_insn (\"st.w r11, 16[sp]\", operands);
- output_asm_insn (\"st.w r10, 12[sp]\", operands);
- output_asm_insn (\"st.w ep, 0[sp]\", operands);
- output_asm_insn (\"st.w gp, 4[sp]\", operands);
- output_asm_insn (\"st.w r1, 8[sp]\", operands);
- output_asm_insn (\"movhi hi(__ep), r0, ep\", operands);
- output_asm_insn (\"movea lo(__ep), ep, ep\", operands);
- output_asm_insn (\"movhi hi(__gp), r0, gp\", operands);
- output_asm_insn (\"movea lo(__gp), gp, gp\", operands);
- return \"\";
+ output_asm_insn ("addi -20, sp, sp", operands);
+ output_asm_insn ("st.w r11, 16[sp]", operands);
+ output_asm_insn ("st.w r10, 12[sp]", operands);
+ output_asm_insn ("st.w ep, 0[sp]", operands);
+ output_asm_insn ("st.w gp, 4[sp]", operands);
+ output_asm_insn ("st.w r1, 8[sp]", operands);
+ output_asm_insn ("movhi hi(__ep), r0, ep", operands);
+ output_asm_insn ("movea lo(__ep), ep, ep", operands);
+ output_asm_insn ("movhi hi(__gp), r0, gp", operands);
+ output_asm_insn ("movea lo(__gp), gp, gp", operands);
+ return "";
}
-}"
+}
[(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 10)
(set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
(set (reg:SI 30) (mem:SI (reg:SI 3)))]
""
- "*
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
- return \"jr __return_interrupt\";
+ return "jr __return_interrupt";
else
{
- output_asm_insn (\"ld.w 0[sp], ep\", operands);
- output_asm_insn (\"ld.w 4[sp], gp\", operands);
- output_asm_insn (\"ld.w 8[sp], r1\", operands);
- output_asm_insn (\"ld.w 12[sp], r10\", operands);
- output_asm_insn (\"ld.w 16[sp], r11\", operands);
- output_asm_insn (\"addi 20, sp, sp\", operands);
- output_asm_insn (\"reti\", operands);
- return \"\";
+ output_asm_insn ("ld.w 0[sp], ep", operands);
+ output_asm_insn ("ld.w 4[sp], gp", operands);
+ output_asm_insn ("ld.w 8[sp], r1", operands);
+ output_asm_insn ("ld.w 12[sp], r10", operands);
+ output_asm_insn ("ld.w 16[sp], r11", operands);
+ output_asm_insn ("addi 20, sp, sp", operands);
+ output_asm_insn ("reti", operands);
+ return "";
}
-}"
+}
[(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4)
(define_insn "save_all_interrupt"
[(unspec_volatile [(const_int 0)] 0)]
""
- "*
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
- return \"jarl __save_all_interrupt,r10\";
+ return "jarl __save_all_interrupt,r10";
- output_asm_insn (\"addi -120, sp, sp\", operands);
+ output_asm_insn ("addi -120, sp, sp", operands);
if (TARGET_EP)
{
- output_asm_insn (\"mov ep, r1\", operands);
- output_asm_insn (\"mov sp, ep\", operands);
- output_asm_insn (\"sst.w r31, 116[ep]\", operands);
- output_asm_insn (\"sst.w r2, 112[ep]\", operands);
- output_asm_insn (\"sst.w gp, 108[ep]\", operands);
- output_asm_insn (\"sst.w r6, 104[ep]\", operands);
- output_asm_insn (\"sst.w r7, 100[ep]\", operands);
- output_asm_insn (\"sst.w r8, 96[ep]\", operands);
- output_asm_insn (\"sst.w r9, 92[ep]\", operands);
- output_asm_insn (\"sst.w r11, 88[ep]\", operands);
- output_asm_insn (\"sst.w r12, 84[ep]\", operands);
- output_asm_insn (\"sst.w r13, 80[ep]\", operands);
- output_asm_insn (\"sst.w r14, 76[ep]\", operands);
- output_asm_insn (\"sst.w r15, 72[ep]\", operands);
- output_asm_insn (\"sst.w r16, 68[ep]\", operands);
- output_asm_insn (\"sst.w r17, 64[ep]\", operands);
- output_asm_insn (\"sst.w r18, 60[ep]\", operands);
- output_asm_insn (\"sst.w r19, 56[ep]\", operands);
- output_asm_insn (\"sst.w r20, 52[ep]\", operands);
- output_asm_insn (\"sst.w r21, 48[ep]\", operands);
- output_asm_insn (\"sst.w r22, 44[ep]\", operands);
- output_asm_insn (\"sst.w r23, 40[ep]\", operands);
- output_asm_insn (\"sst.w r24, 36[ep]\", operands);
- output_asm_insn (\"sst.w r25, 32[ep]\", operands);
- output_asm_insn (\"sst.w r26, 28[ep]\", operands);
- output_asm_insn (\"sst.w r27, 24[ep]\", operands);
- output_asm_insn (\"sst.w r28, 20[ep]\", operands);
- output_asm_insn (\"sst.w r29, 16[ep]\", operands);
- output_asm_insn (\"mov r1, ep\", operands);
+ output_asm_insn ("mov ep, r1", operands);
+ output_asm_insn ("mov sp, ep", operands);
+ output_asm_insn ("sst.w r31, 116[ep]", operands);
+ output_asm_insn ("sst.w r2, 112[ep]", operands);
+ output_asm_insn ("sst.w gp, 108[ep]", operands);
+ output_asm_insn ("sst.w r6, 104[ep]", operands);
+ output_asm_insn ("sst.w r7, 100[ep]", operands);
+ output_asm_insn ("sst.w r8, 96[ep]", operands);
+ output_asm_insn ("sst.w r9, 92[ep]", operands);
+ output_asm_insn ("sst.w r11, 88[ep]", operands);
+ output_asm_insn ("sst.w r12, 84[ep]", operands);
+ output_asm_insn ("sst.w r13, 80[ep]", operands);
+ output_asm_insn ("sst.w r14, 76[ep]", operands);
+ output_asm_insn ("sst.w r15, 72[ep]", operands);
+ output_asm_insn ("sst.w r16, 68[ep]", operands);
+ output_asm_insn ("sst.w r17, 64[ep]", operands);
+ output_asm_insn ("sst.w r18, 60[ep]", operands);
+ output_asm_insn ("sst.w r19, 56[ep]", operands);
+ output_asm_insn ("sst.w r20, 52[ep]", operands);
+ output_asm_insn ("sst.w r21, 48[ep]", operands);
+ output_asm_insn ("sst.w r22, 44[ep]", operands);
+ output_asm_insn ("sst.w r23, 40[ep]", operands);
+ output_asm_insn ("sst.w r24, 36[ep]", operands);
+ output_asm_insn ("sst.w r25, 32[ep]", operands);
+ output_asm_insn ("sst.w r26, 28[ep]", operands);
+ output_asm_insn ("sst.w r27, 24[ep]", operands);
+ output_asm_insn ("sst.w r28, 20[ep]", operands);
+ output_asm_insn ("sst.w r29, 16[ep]", operands);
+ output_asm_insn ("mov r1, ep", operands);
}
else
{
- output_asm_insn (\"st.w r31, 116[sp]\", operands);
- output_asm_insn (\"st.w r2, 112[sp]\", operands);
- output_asm_insn (\"st.w gp, 108[sp]\", operands);
- output_asm_insn (\"st.w r6, 104[sp]\", operands);
- output_asm_insn (\"st.w r7, 100[sp]\", operands);
- output_asm_insn (\"st.w r8, 96[sp]\", operands);
- output_asm_insn (\"st.w r9, 92[sp]\", operands);
- output_asm_insn (\"st.w r11, 88[sp]\", operands);
- output_asm_insn (\"st.w r12, 84[sp]\", operands);
- output_asm_insn (\"st.w r13, 80[sp]\", operands);
- output_asm_insn (\"st.w r14, 76[sp]\", operands);
- output_asm_insn (\"st.w r15, 72[sp]\", operands);
- output_asm_insn (\"st.w r16, 68[sp]\", operands);
- output_asm_insn (\"st.w r17, 64[sp]\", operands);
- output_asm_insn (\"st.w r18, 60[sp]\", operands);
- output_asm_insn (\"st.w r19, 56[sp]\", operands);
- output_asm_insn (\"st.w r20, 52[sp]\", operands);
- output_asm_insn (\"st.w r21, 48[sp]\", operands);
- output_asm_insn (\"st.w r22, 44[sp]\", operands);
- output_asm_insn (\"st.w r23, 40[sp]\", operands);
- output_asm_insn (\"st.w r24, 36[sp]\", operands);
- output_asm_insn (\"st.w r25, 32[sp]\", operands);
- output_asm_insn (\"st.w r26, 28[sp]\", operands);
- output_asm_insn (\"st.w r27, 24[sp]\", operands);
- output_asm_insn (\"st.w r28, 20[sp]\", operands);
- output_asm_insn (\"st.w r29, 16[sp]\", operands);
+ output_asm_insn ("st.w r31, 116[sp]", operands);
+ output_asm_insn ("st.w r2, 112[sp]", operands);
+ output_asm_insn ("st.w gp, 108[sp]", operands);
+ output_asm_insn ("st.w r6, 104[sp]", operands);
+ output_asm_insn ("st.w r7, 100[sp]", operands);
+ output_asm_insn ("st.w r8, 96[sp]", operands);
+ output_asm_insn ("st.w r9, 92[sp]", operands);
+ output_asm_insn ("st.w r11, 88[sp]", operands);
+ output_asm_insn ("st.w r12, 84[sp]", operands);
+ output_asm_insn ("st.w r13, 80[sp]", operands);
+ output_asm_insn ("st.w r14, 76[sp]", operands);
+ output_asm_insn ("st.w r15, 72[sp]", operands);
+ output_asm_insn ("st.w r16, 68[sp]", operands);
+ output_asm_insn ("st.w r17, 64[sp]", operands);
+ output_asm_insn ("st.w r18, 60[sp]", operands);
+ output_asm_insn ("st.w r19, 56[sp]", operands);
+ output_asm_insn ("st.w r20, 52[sp]", operands);
+ output_asm_insn ("st.w r21, 48[sp]", operands);
+ output_asm_insn ("st.w r22, 44[sp]", operands);
+ output_asm_insn ("st.w r23, 40[sp]", operands);
+ output_asm_insn ("st.w r24, 36[sp]", operands);
+ output_asm_insn ("st.w r25, 32[sp]", operands);
+ output_asm_insn ("st.w r26, 28[sp]", operands);
+ output_asm_insn ("st.w r27, 24[sp]", operands);
+ output_asm_insn ("st.w r28, 20[sp]", operands);
+ output_asm_insn ("st.w r29, 16[sp]", operands);
}
- return \"\";
-}"
+ return "";
+}
[(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4)
(define_insn "restore_all_interrupt"
[(unspec_volatile [(const_int 0)] 1)]
""
- "*
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
- return \"jarl __restore_all_interrupt,r10\";
+ return "jarl __restore_all_interrupt,r10";
if (TARGET_EP)
{
- output_asm_insn (\"mov ep, r1\", operands);
- output_asm_insn (\"mov sp, ep\", operands);
- output_asm_insn (\"sld.w 116[ep], r31\", operands);
- output_asm_insn (\"sld.w 112[ep], r2\", operands);
- output_asm_insn (\"sld.w 108[ep], gp\", operands);
- output_asm_insn (\"sld.w 104[ep], r6\", operands);
- output_asm_insn (\"sld.w 100[ep], r7\", operands);
- output_asm_insn (\"sld.w 96[ep], r8\", operands);
- output_asm_insn (\"sld.w 92[ep], r9\", operands);
- output_asm_insn (\"sld.w 88[ep], r11\", operands);
- output_asm_insn (\"sld.w 84[ep], r12\", operands);
- output_asm_insn (\"sld.w 80[ep], r13\", operands);
- output_asm_insn (\"sld.w 76[ep], r14\", operands);
- output_asm_insn (\"sld.w 72[ep], r15\", operands);
- output_asm_insn (\"sld.w 68[ep], r16\", operands);
- output_asm_insn (\"sld.w 64[ep], r17\", operands);
- output_asm_insn (\"sld.w 60[ep], r18\", operands);
- output_asm_insn (\"sld.w 56[ep], r19\", operands);
- output_asm_insn (\"sld.w 52[ep], r20\", operands);
- output_asm_insn (\"sld.w 48[ep], r21\", operands);
- output_asm_insn (\"sld.w 44[ep], r22\", operands);
- output_asm_insn (\"sld.w 40[ep], r23\", operands);
- output_asm_insn (\"sld.w 36[ep], r24\", operands);
- output_asm_insn (\"sld.w 32[ep], r25\", operands);
- output_asm_insn (\"sld.w 28[ep], r26\", operands);
- output_asm_insn (\"sld.w 24[ep], r27\", operands);
- output_asm_insn (\"sld.w 20[ep], r28\", operands);
- output_asm_insn (\"sld.w 16[ep], r29\", operands);
- output_asm_insn (\"mov r1, ep\", operands);
+ output_asm_insn ("mov ep, r1", operands);
+ output_asm_insn ("mov sp, ep", operands);
+ output_asm_insn ("sld.w 116[ep], r31", operands);
+ output_asm_insn ("sld.w 112[ep], r2", operands);
+ output_asm_insn ("sld.w 108[ep], gp", operands);
+ output_asm_insn ("sld.w 104[ep], r6", operands);
+ output_asm_insn ("sld.w 100[ep], r7", operands);
+ output_asm_insn ("sld.w 96[ep], r8", operands);
+ output_asm_insn ("sld.w 92[ep], r9", operands);
+ output_asm_insn ("sld.w 88[ep], r11", operands);
+ output_asm_insn ("sld.w 84[ep], r12", operands);
+ output_asm_insn ("sld.w 80[ep], r13", operands);
+ output_asm_insn ("sld.w 76[ep], r14", operands);
+ output_asm_insn ("sld.w 72[ep], r15", operands);
+ output_asm_insn ("sld.w 68[ep], r16", operands);
+ output_asm_insn ("sld.w 64[ep], r17", operands);
+ output_asm_insn ("sld.w 60[ep], r18", operands);
+ output_asm_insn ("sld.w 56[ep], r19", operands);
+ output_asm_insn ("sld.w 52[ep], r20", operands);
+ output_asm_insn ("sld.w 48[ep], r21", operands);
+ output_asm_insn ("sld.w 44[ep], r22", operands);
+ output_asm_insn ("sld.w 40[ep], r23", operands);
+ output_asm_insn ("sld.w 36[ep], r24", operands);
+ output_asm_insn ("sld.w 32[ep], r25", operands);
+ output_asm_insn ("sld.w 28[ep], r26", operands);
+ output_asm_insn ("sld.w 24[ep], r27", operands);
+ output_asm_insn ("sld.w 20[ep], r28", operands);
+ output_asm_insn ("sld.w 16[ep], r29", operands);
+ output_asm_insn ("mov r1, ep", operands);
}
else
{
- output_asm_insn (\"ld.w 116[sp], r31\", operands);
- output_asm_insn (\"ld.w 112[sp], r2\", operands);
- output_asm_insn (\"ld.w 108[sp], gp\", operands);
- output_asm_insn (\"ld.w 104[sp], r6\", operands);
- output_asm_insn (\"ld.w 100[sp], r7\", operands);
- output_asm_insn (\"ld.w 96[sp], r8\", operands);
- output_asm_insn (\"ld.w 92[sp], r9\", operands);
- output_asm_insn (\"ld.w 88[sp], r11\", operands);
- output_asm_insn (\"ld.w 84[sp], r12\", operands);
- output_asm_insn (\"ld.w 80[sp], r13\", operands);
- output_asm_insn (\"ld.w 76[sp], r14\", operands);
- output_asm_insn (\"ld.w 72[sp], r15\", operands);
- output_asm_insn (\"ld.w 68[sp], r16\", operands);
- output_asm_insn (\"ld.w 64[sp], r17\", operands);
- output_asm_insn (\"ld.w 60[sp], r18\", operands);
- output_asm_insn (\"ld.w 56[sp], r19\", operands);
- output_asm_insn (\"ld.w 52[sp], r20\", operands);
- output_asm_insn (\"ld.w 48[sp], r21\", operands);
- output_asm_insn (\"ld.w 44[sp], r22\", operands);
- output_asm_insn (\"ld.w 40[sp], r23\", operands);
- output_asm_insn (\"ld.w 36[sp], r24\", operands);
- output_asm_insn (\"ld.w 32[sp], r25\", operands);
- output_asm_insn (\"ld.w 28[sp], r26\", operands);
- output_asm_insn (\"ld.w 24[sp], r27\", operands);
- output_asm_insn (\"ld.w 20[sp], r28\", operands);
- output_asm_insn (\"ld.w 16[sp], r29\", operands);
+ output_asm_insn ("ld.w 116[sp], r31", operands);
+ output_asm_insn ("ld.w 112[sp], r2", operands);
+ output_asm_insn ("ld.w 108[sp], gp", operands);
+ output_asm_insn ("ld.w 104[sp], r6", operands);
+ output_asm_insn ("ld.w 100[sp], r7", operands);
+ output_asm_insn ("ld.w 96[sp], r8", operands);
+ output_asm_insn ("ld.w 92[sp], r9", operands);
+ output_asm_insn ("ld.w 88[sp], r11", operands);
+ output_asm_insn ("ld.w 84[sp], r12", operands);
+ output_asm_insn ("ld.w 80[sp], r13", operands);
+ output_asm_insn ("ld.w 76[sp], r14", operands);
+ output_asm_insn ("ld.w 72[sp], r15", operands);
+ output_asm_insn ("ld.w 68[sp], r16", operands);
+ output_asm_insn ("ld.w 64[sp], r17", operands);
+ output_asm_insn ("ld.w 60[sp], r18", operands);
+ output_asm_insn ("ld.w 56[sp], r19", operands);
+ output_asm_insn ("ld.w 52[sp], r20", operands);
+ output_asm_insn ("ld.w 48[sp], r21", operands);
+ output_asm_insn ("ld.w 44[sp], r22", operands);
+ output_asm_insn ("ld.w 40[sp], r23", operands);
+ output_asm_insn ("ld.w 36[sp], r24", operands);
+ output_asm_insn ("ld.w 32[sp], r25", operands);
+ output_asm_insn ("ld.w 28[sp], r26", operands);
+ output_asm_insn ("ld.w 24[sp], r27", operands);
+ output_asm_insn ("ld.w 20[sp], r28", operands);
+ output_asm_insn ("ld.w 16[sp], r29", operands);
}
- output_asm_insn (\"addi 120, sp, sp\", operands);
- return \"\";
-}"
+ output_asm_insn ("addi 120, sp, sp", operands);
+ return "";
+}
[(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4)
projects / thirdparty / gcc.git / commitdiff
