5.15-stable patches

added patches:
	arm64-subscribe-microsoft-azure-cobalt-100-to-arm-neoverse-n2-errata.patch

diff --git a/queue-5.15/arm64-subscribe-microsoft-azure-cobalt-100-to-arm-neoverse-n2-errata.patch b/queue-5.15/arm64-subscribe-microsoft-azure-cobalt-100-to-arm-neoverse-n2-errata.patch
new file mode 100644 (file)
index 0000000..610dfc8
--- /dev/null
+++ b/queue-5.15/arm64-subscribe-microsoft-azure-cobalt-100-to-arm-neoverse-n2-errata.patch
@@ -0,0 +1,95 @@
+From fb091ff394792c018527b3211bbdfae93ea4ac02 Mon Sep 17 00:00:00 2001
+From: Easwar Hariharan <eahariha@linux.microsoft.com>
+Date: Wed, 14 Feb 2024 17:55:18 +0000
+Subject: arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
+
+From: Easwar Hariharan <eahariha@linux.microsoft.com>
+
+commit fb091ff394792c018527b3211bbdfae93ea4ac02 upstream.
+
+Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
+implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
+suffers from all the same errata.
+
+CC: stable@vger.kernel.org # 5.15+
+Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
+Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
+Acked-by: Mark Rutland <mark.rutland@arm.com>
+Acked-by: Marc Zyngier <maz@kernel.org>
+Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
+Link: https://lore.kernel.org/r/20240214175522.2457857-1-eahariha@linux.microsoft.com
+Signed-off-by: Will Deacon <will@kernel.org>
+Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ Documentation/arm64/silicon-errata.rst |    7 +++++++
+ arch/arm64/include/asm/cputype.h       |    4 ++++
+ arch/arm64/kernel/cpu_errata.c         |    3 +++
+ 3 files changed, 14 insertions(+)
+
+--- a/Documentation/arm64/silicon-errata.rst
++++ b/Documentation/arm64/silicon-errata.rst
+@@ -198,3 +198,10 @@ stable kernels.
+ +----------------+-----------------+-----------------+-----------------------------+
+ | Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |
+ +----------------+-----------------+-----------------+-----------------------------+
+++----------------+-----------------+-----------------+-----------------------------+
++| Microsoft      | Azure Cobalt 100| #2139208        | ARM64_ERRATUM_2139208       |
+++----------------+-----------------+-----------------+-----------------------------+
++| Microsoft      | Azure Cobalt 100| #2067961        | ARM64_ERRATUM_2067961       |
+++----------------+-----------------+-----------------+-----------------------------+
++| Microsoft      | Azure Cobalt 100| #2253138        | ARM64_ERRATUM_2253138       |
+++----------------+-----------------+-----------------+-----------------------------+
+--- a/arch/arm64/include/asm/cputype.h
++++ b/arch/arm64/include/asm/cputype.h
+@@ -61,6 +61,7 @@
+ #define ARM_CPU_IMP_HISI              0x48
+ #define ARM_CPU_IMP_APPLE             0x61
+ #define ARM_CPU_IMP_AMPERE            0xC0
++#define ARM_CPU_IMP_MICROSOFT         0x6D
+ 
+ #define ARM_CPU_PART_AEM_V8           0xD0F
+ #define ARM_CPU_PART_FOUNDATION               0xD00
+@@ -116,6 +117,8 @@
+ 
+ #define AMPERE_CPU_PART_AMPERE1               0xAC3
+ 
++#define MICROSOFT_CPU_PART_AZURE_COBALT_100   0xD49 /* Based on r0p0 of ARM Neoverse N2 */
++
+ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
+ #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
+ #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
+@@ -157,6 +160,7 @@
+ #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
+ #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
+ #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
++#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
+ 
+ /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
+ #define MIDR_FUJITSU_ERRATUM_010001           MIDR_FUJITSU_A64FX
+--- a/arch/arm64/kernel/cpu_errata.c
++++ b/arch/arm64/kernel/cpu_errata.c
+@@ -367,6 +367,7 @@ static struct midr_range broken_aarch32_
+ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
+ #ifdef CONFIG_ARM64_ERRATUM_2139208
+       MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
++      MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
+ #endif
+ #ifdef CONFIG_ARM64_ERRATUM_2119858
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+@@ -379,6 +380,7 @@ static const struct midr_range trbe_over
+ static const struct midr_range tsb_flush_fail_cpus[] = {
+ #ifdef CONFIG_ARM64_ERRATUM_2067961
+       MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
++      MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
+ #endif
+ #ifdef CONFIG_ARM64_ERRATUM_2054223
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+@@ -391,6 +393,7 @@ static const struct midr_range tsb_flush
+ static struct midr_range trbe_write_out_of_range_cpus[] = {
+ #ifdef CONFIG_ARM64_ERRATUM_2253138
+       MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
++      MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
+ #endif
+ #ifdef CONFIG_ARM64_ERRATUM_2224489
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

diff --git a/queue-5.15/series b/queue-5.15/series
index 46ace0fa816a8b73b3e2fb3499ddcd099e1e2029..e1cb32fafafc48a0bd5c2e0a91b4f8d1097b236c 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -465,3 +465,4 @@ sched-membarrier-reduce-the-ability-to-hammer-on-sys_membarrier.patch
 nilfs2-fix-potential-bug-in-end_buffer_async_write.patch
 nilfs2-replace-warn_ons-for-invalid-dat-metadata-block-requests.patch
 dm-limit-the-number-of-targets-and-parameter-size-area.patch
+arm64-subscribe-microsoft-azure-cobalt-100-to-arm-neoverse-n2-errata.patch