[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): New def.
	(RISCV_CORE): Ditto.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
	option.
	* config/riscv/riscv.cc: New def.
	* config/riscv/riscv.md: New include.
	* config/riscv/xiangshan.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test.

	Co-Authored by: Lin Jiawei <jiawei.lin@epfl.ch>

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 57928bccdc826f7dd3e15fd17b156935d8178858..2f5efe3be86a633136899f57765e877eae6dfb12 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -40,6 +40,7 @@ RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
 RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
 
@@ -90,4 +91,9 @@ RISCV_CORE("thead-c906",      "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
                              "xtheadcondmov_xtheadfmemidx_xtheadmac_"
                              "xtheadmemidx_xtheadmempair_xtheadsync",
                              "thead-c906")
+
+RISCV_CORE("xiangshan-nanhu",      "rv64imafdc_zba_zbb_zbc_zbs_"
+                             "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
+                             "svinval_zicbom_zicboz",
+                             "xiangshan-nanhu")
 #undef RISCV_CORE

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 281dd068c55faf04e8c6843706acf155cd323e04..9ae86d52a75fdad4904261b9af560dfa4fb48287 100644 (file)
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -57,6 +57,7 @@ enum riscv_microarchitecture_type {
   sifive_7,
   sifive_p400,
   sifive_p600,
+  xiangshan,
   generic_ooo
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 680c4a728e924fcf625932b4495ec51a2a184809..45015addd1feb031234554251123aaec9ce63850 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -498,6 +498,23 @@ static const struct riscv_tune_param thead_c906_tune_info = {
   NULL,                                                /* vector cost */
 };
 
+/* Costs to use when optimizing for xiangshan nanhu.  */
+static const struct riscv_tune_param xiangshan_nanhu_tune_info = {
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},      /* fp_add */
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},      /* fp_mul */
+  {COSTS_N_INSNS (10), COSTS_N_INSNS (20)},    /* fp_div */
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},      /* int_mul */
+  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},      /* int_div */
+  6,                                           /* issue_rate */
+  3,                                           /* branch_cost */
+  3,                                           /* memory_cost */
+  3,                                           /* fmv_cost */
+  true,                                                /* slow_unaligned_access */
+  false,                                       /* use_divmod_expansion */
+  RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH,          /* fusible_ops */
+  NULL,                                                /* vector cost */
+};
+
 /* Costs to use when optimizing for a generic ooo profile.  */
 static const struct riscv_tune_param generic_ooo_tune_info = {
   {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},      /* fp_add */

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b16ed97909c04456ce4fe5234a82c5597549b67d..f433b03885cc8487401e454d69f796db59a63a88 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -685,7 +685,7 @@
 ;; Microarchitectures we know how to tune for.
 ;; Keep this in sync with enum riscv_microarchitecture.
 (define_attr "tune"
-  "generic,sifive_7,sifive_p400,sifive_p600,generic_ooo"
+  "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo"
   (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
 
 ;; Describe a user's asm statement.
@@ -3859,3 +3859,4 @@
 (include "sfb.md")
 (include "zc.md")
 (include "corev.md")
+(include "xiangshan.md")

diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
new file mode 100644 (file)
index 0000000..381c3ce
--- /dev/null
+++ b/gcc/config/riscv/xiangshan.md
@@ -0,0 +1,148 @@
+;; Scheduling description for XiangShan Nanhu.
+
+;; Nanhu is a 6-issue, superscalar, out-of-order processor.
+
+;; -----------------------------------------------------
+;; Nanhu Core units
+;; 1*jmp + 4*alu + 2*mdu + 4*fma + 2*fmisc + 2*ld + 2*st
+;; -----------------------------------------------------
+
+(define_automaton "xiangshan")
+
+(define_cpu_unit "xs_jmp" "xiangshan")
+(define_cpu_unit "xs_i2f" "xiangshan")
+(define_reservation "xs_jmp_rs" "xs_jmp | xs_i2f")
+
+(define_cpu_unit "xs_alu_0, xs_alu_1, xs_alu_2, xs_alu_3" "xiangshan")
+(define_reservation "xs_alu_rs"
+  "xs_alu_0 | xs_alu_1 | xs_alu_2 | xs_alu_3")
+
+(define_cpu_unit "xs_mul_0, xs_mul_1" "xiangshan")
+(define_cpu_unit "xs_div_0, xs_div_1" "xiangshan")
+(define_reservation "xs_mdu_rs"
+  "(xs_mul_0 + xs_div_0) | (xs_mul_1 + xs_div_1)")
+
+(define_cpu_unit "xs_fadd_0, xs_fadd_1, xs_fadd_2, xs_fadd_3" "xiangshan")
+(define_cpu_unit "xs_fmul_0, xs_fmul_1, xs_fmul_2, xs_fmul_3" "xiangshan")
+(define_reservation "xs_fma_0" "xs_fadd_0 + xs_fmul_0")
+(define_reservation "xs_fma_1" "xs_fadd_1 + xs_fmul_1")
+(define_reservation "xs_fma_2" "xs_fadd_2 + xs_fmul_2")
+(define_reservation "xs_fma_3" "xs_fadd_3 + xs_fmul_3")
+
+(define_cpu_unit "xs_f2f_0, xs_f2f_1" "xiangshan")
+(define_cpu_unit "xs_f2i_0, xs_f2i_1" "xiangshan")
+(define_cpu_unit "xs_fdiv_0, xs_fdiv_1" "xiangshan")
+(define_reservation "xs_fmisc_rs"
+  "(xs_f2f_0 + xs_f2i_0 + xs_fdiv_0) | (xs_f2f_1 + xs_f2i_1 + xs_fdiv_1)")
+
+(define_cpu_unit "xs_ld_0, xs_ld_1" "xiangshan")
+(define_cpu_unit "xs_st_0, xs_st_1" "xiangshan")
+(define_reservation "xs_ld_rs" "xs_ld_0 | xs_ld_1")
+(define_reservation "xs_st_rs" "xs_st_0 | xs_st_1")
+
+;; ----------------------------------------------------
+;; Memory (load/store)
+;; ----------------------------------------------------
+
+(define_insn_reservation "xiangshan_load" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "load"))
+  "xs_ld_rs")
+
+(define_insn_reservation "xiangshan_fpload" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fpload"))
+  "xs_ld_rs")
+
+(define_insn_reservation "xiangshan_store" 1
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "store"))
+  "xs_st_rs")
+
+(define_insn_reservation "xiangshan_fpstore" 1
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fpstore"))
+  "xs_st_rs")
+
+;; ----------------------------------------------------
+;; Int
+;; ----------------------------------------------------
+
+(define_insn_reservation "xiangshan_jump" 1
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "jump,call,auipc,unknown"))
+  "xs_jmp_rs")
+
+(define_insn_reservation "xiangshan_i2f" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "mtc"))
+  "xs_jmp_rs")
+
+(define_insn_reservation "xiangshan_mul" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "imul"))
+  "xs_mdu_rs")
+
+(define_insn_reservation "xiangshan_div" 21
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "idiv"))
+  "xs_mdu_rs")
+
+(define_insn_reservation "xiangshan_alu" 1
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "nop,const,branch,arith,shift,slt,multi,logical,move,bitmanip,unknown"))
+  "xs_alu_rs")
+
+;; ----------------------------------------------------
+;; Float
+;; ----------------------------------------------------
+
+
+(define_insn_reservation "xiangshan_fma" 5
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fmadd"))
+  "xs_fma_0 | xs_fma_1 | xs_fma_2 | xs_fma_3")
+
+(define_insn_reservation "xiangshan_fadd" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fadd"))
+  "xs_fadd_0 | xs_fadd_1 | xs_fadd_2 | xs_fadd_3")
+
+(define_insn_reservation "xiangshan_fmul" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fmul"))
+  "xs_fmul_0 | xs_fmul_1 | xs_fmul_2 | xs_fmul_3")
+
+(define_insn_reservation "xiangshan_f2f" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fcvt,fmove"))
+  "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_f2i" 3
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "mfc,fcmp"))
+  "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_sfdiv" 11
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fdiv")
+       (eq_attr "mode" "SF"))
+  "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_sfsqrt" 17
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fsqrt")
+       (eq_attr "mode" "SF"))
+  "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_dfdiv" 21
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fdiv")
+       (eq_attr "mode" "DF"))
+  "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_dfsqrt" 37
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "fsqrt")
+       (eq_attr "mode" "DF"))
+  "xs_fmisc_rs")

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c
new file mode 100644 (file)
index 0000000..2903c88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xiangshan-nanhu" { target { rv64 } } } */
+/* XiangShan Nanhu => rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd
+                      _zkne_zknh_zksed_zksh_svinval_zicbom_zicboz */
+
+#if !((__riscv_xlen == 64)             \
+      && !defined(__riscv_32e)         \
+      && defined(__riscv_mul)          \
+      && defined(__riscv_atomic)       \
+      && (__riscv_flen == 64)          \
+      && defined(__riscv_compressed)   \
+      && defined(__riscv_zicbom)       \
+      && defined(__riscv_zicboz)       \
+      && defined(__riscv_zba)  \
+      && defined(__riscv_zbb)  \
+      && defined(__riscv_zbc)  \
+      && defined(__riscv_zbs)  \
+      && defined(__riscv_zbkb) \
+      && defined(__riscv_zbkc) \
+      && defined(__riscv_zbkx) \
+      && defined(__riscv_zknd) \
+      && defined(__riscv_zkne) \
+      && defined(__riscv_zknh) \
+      && defined(__riscv_zksed)        \
+      && defined(__riscv_zksh) \
+      && defined(__riscv_svinval))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+  return 0;
+}