(API-visible change): generalise the VexSubArch idea. Everywhere

where a VexSubArch was previously passed around, a VexArchInfo is now
passed around.  This is a struct which carries more details about any
given architecture and in particular gives a clean way to pass around
info about PPC cache line sizes, which is needed for guest-side PPC.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1233

diff --git a/VEX/priv/guest-amd64/gdefs.h b/VEX/priv/guest-amd64/gdefs.h
index 6279014318c6beb27a0d88d14173cbdd285927ec..d1f9c2001618066de653546c87272b73d893ce66 100644 (file)
--- a/VEX/priv/guest-amd64/gdefs.h
+++ b/VEX/priv/guest-amd64/gdefs.h
@@ -50,7 +50,7 @@ IRBB* bbToIR_AMD64 ( UChar*           amd64code,
                      Bool             (*byte_accessible)(Addr64),
                      Bool             (*resteerOkFn)(Addr64),
                      Bool             host_bigendian,
-                     VexSubArch       subarch_guest );
+                     VexArchInfo*     archinfo_guest );
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern

diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c
index c4d1815cca7cbb0f54eade6f8a684a19d1943286..0c2adb41cc01a0195cca2185d9d5e61adc99a696 100644 (file)
--- a/VEX/priv/guest-amd64/toIR.c
+++ b/VEX/priv/guest-amd64/toIR.c
@@ -398,12 +398,12 @@ typedef
    resteer into, returns False.  */
    
 static 
-DisResult disInstr ( /*IN*/  Bool       resteerOK,
-                     /*IN*/  Bool       (*resteerOkFn) ( Addr64 ),
-                     /*IN*/  ULong      delta, 
-                     /*IN*/  VexSubArch subarch,
-                     /*OUT*/ Long*      size,
-                     /*OUT*/ Addr64*    whereNext );
+DisResult disInstr ( /*IN*/  Bool         resteerOK,
+                     /*IN*/  Bool         (*resteerOkFn) ( Addr64 ),
+                     /*IN*/  ULong        delta, 
+                     /*IN*/  VexArchInfo* archinfo,
+                     /*OUT*/ Long*        size,
+                     /*OUT*/ Addr64*      whereNext );
 
 
 /* This is the main (only, in fact) entry point for this module. */
@@ -417,7 +417,7 @@ IRBB* bbToIR_AMD64 ( UChar*           amd64code,
                      Bool             (*byte_accessible)(Addr64),
                      Bool             (*chase_into_ok)(Addr64),
                      Bool             host_bigendian,
-                     VexSubArch       subarch_guest )
+                     VexArchInfo*     archinfo_guest )
 {
    Long       delta, size;
    Int        i, n_instrs, first_stmt_idx;
@@ -434,7 +434,7 @@ IRBB* bbToIR_AMD64 ( UChar*           amd64code,
    vassert(vex_control.guest_chase_thresh >= 0);
    vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns);
 
-   vassert(subarch_guest == VexSubArch_NONE);
+   vassert(archinfo_guest->subarch == VexSubArch_NONE);
 
    /* Start a new, empty extent. */
    vge->n_used  = 1;
@@ -491,7 +491,7 @@ IRBB* bbToIR_AMD64 ( UChar*           amd64code,
       guest_rip_next_assumed = 0;
       guest_rip_next_mustcheck = False;
       dres = disInstr( resteerOK, chase_into_ok, 
-                       delta, subarch_guest, &size, &guest_next );
+                       delta, archinfo_guest, &size, &guest_next );
       insn_verbose = False;
 
       /* stay sane ... */
@@ -7927,12 +7927,12 @@ static IRExpr* mk64from16s ( IRTemp t3, IRTemp t2,
    is False, disInstr may not return Dis_Resteer. */
    
 static 
-DisResult disInstr ( /*IN*/  Bool       resteerOK,
-                     /*IN*/  Bool       (*resteerOkFn) ( Addr64 ),
-                     /*IN*/  ULong      delta, 
-                     /*IN*/  VexSubArch subarch,
-                     /*OUT*/ Long*      size,
-                     /*OUT*/ Addr64*    whereNext )
+DisResult disInstr ( /*IN*/  Bool         resteerOK,
+                     /*IN*/  Bool         (*resteerOkFn) ( Addr64 ),
+                     /*IN*/  ULong        delta, 
+                     /*IN*/  VexArchInfo* archinfo,
+                     /*OUT*/ Long*        size,
+                     /*OUT*/ Addr64*      whereNext )
 {
    IRType    ty;
    IRTemp    addr, t0, t1, t2, t3, t4, t5, t6;
@@ -13115,7 +13115,7 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
          HChar*   fName = NULL;
          void*    fAddr = NULL;
          if (haveF2orF3(pfx)) goto decode_failure;
-         switch (subarch) {
+         switch (archinfo->subarch) {
             case VexSubArch_NONE:
                fName = "amd64g_dirtyhelper_CPUID";
                fAddr = &amd64g_dirtyhelper_CPUID; 

diff --git a/VEX/priv/guest-ppc32/gdefs.h b/VEX/priv/guest-ppc32/gdefs.h
index 30b3f204f97e247ff758109fdf23d49bf51ade43..4a8161f60c829c6be7cedf7a8804766db181f6ba 100644 (file)
--- a/VEX/priv/guest-ppc32/gdefs.h
+++ b/VEX/priv/guest-ppc32/gdefs.h
@@ -69,7 +69,7 @@ IRBB* bbToIR_PPC32 ( UChar*           ppc32code,
                      Bool             (*byte_accessible)(Addr64),
                      Bool             (*resteerOkFn)(Addr64),
                      Bool             host_bigendian,
-                     VexSubArch       subarch_guest );
+                     VexArchInfo*     archinfo_guest );
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern

diff --git a/VEX/priv/guest-ppc32/toIR.c b/VEX/priv/guest-ppc32/toIR.c
index a291ebee027c4207d43ebe1b4bcba0db943c3067..f1df79eb7f7b2d7a0c95da15b371dc25386db22b 100644 (file)
--- a/VEX/priv/guest-ppc32/toIR.c
+++ b/VEX/priv/guest-ppc32/toIR.c
@@ -298,7 +298,7 @@ IRBB* bbToIR_PPC32 ( UChar*           ppc32code,
                      Bool             (*byte_accessible)(Addr64),
                      Bool             (*chase_into_ok)(Addr64),
                      Bool             host_bigendian,
-                     VexSubArch       subarch_guest )
+                     VexArchInfo*     archinfo_guest )
 {
    UInt       delta;
    Int        i, n_instrs, size, first_stmt_idx;
@@ -314,8 +314,8 @@ IRBB* bbToIR_PPC32 ( UChar*           ppc32code,
    vassert(vex_control.guest_chase_thresh >= 0);
    vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns);
 
-   vassert(subarch_guest == VexSubArchPPC32_noAV
-           || subarch_guest == VexSubArchPPC32_AV);
+   vassert(archinfo_guest->subarch == VexSubArchPPC32_noAV
+           || archinfo_guest->subarch == VexSubArchPPC32_AV);
 
    /* Start a new, empty extent. */
    vge->n_used  = 1;

diff --git a/VEX/priv/guest-x86/gdefs.h b/VEX/priv/guest-x86/gdefs.h
index 2f58598047f4ba71c2fad0890c57cc341b97911b..29a1fabec7956bed43bb07d39cb35df58740738b 100644 (file)
--- a/VEX/priv/guest-x86/gdefs.h
+++ b/VEX/priv/guest-x86/gdefs.h
@@ -50,7 +50,7 @@ IRBB* bbToIR_X86 ( UChar*           x86code,
                    Bool             (*byte_accessible)(Addr64),
                    Bool             (*resteerOkFn)(Addr64),
                    Bool             host_bigendian,
-                   VexSubArch       subarch_guest );
+                   VexArchInfo*     archinfo_guest );
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern

diff --git a/VEX/priv/guest-x86/toIR.c b/VEX/priv/guest-x86/toIR.c
index ab7de82aa63bd048811e43979ec41e91f19f2c83..7eec4af2a9619dcc5b06666c5a19e2a147d11ec6 100644 (file)
--- a/VEX/priv/guest-x86/toIR.c
+++ b/VEX/priv/guest-x86/toIR.c
@@ -233,12 +233,12 @@ static void stmt ( IRStmt* st );
    resteer into, returns False.  */
    
 static 
-DisResult disInstr ( /*IN*/  Bool       resteerOK,
-                     /*IN*/  Bool       (*resteerOkFn) ( Addr64 ),
-                     /*IN*/  UInt       delta, 
-                     /*IN*/  VexSubArch subarch,
-                     /*OUT*/ Int*       size,
-                     /*OUT*/ Addr64*    whereNext );
+DisResult disInstr ( /*IN*/  Bool         resteerOK,
+                     /*IN*/  Bool         (*resteerOkFn) ( Addr64 ),
+                     /*IN*/  UInt         delta, 
+                     /*IN*/  VexArchInfo* archinfo,
+                     /*OUT*/ Int*         size,
+                     /*OUT*/ Addr64*      whereNext );
 
 
 /* This is the main (only, in fact) entry point for this module. */
@@ -252,7 +252,7 @@ IRBB* bbToIR_X86 ( UChar*           x86code,
                    Bool             (*byte_accessible)(Addr64),
                    Bool             (*chase_into_ok)(Addr64),
                    Bool             host_bigendian,
-                   VexSubArch       subarch_guest )
+                   VexArchInfo*     archinfo_guest )
 {
    UInt       delta;
    Int        i, n_instrs, size, first_stmt_idx;
@@ -269,9 +269,9 @@ IRBB* bbToIR_X86 ( UChar*           x86code,
    vassert(vex_control.guest_chase_thresh >= 0);
    vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns);
 
-   vassert(subarch_guest == VexSubArchX86_sse0
-           || subarch_guest == VexSubArchX86_sse1
-           || subarch_guest == VexSubArchX86_sse2);
+   vassert(archinfo_guest->subarch == VexSubArchX86_sse0
+           || archinfo_guest->subarch == VexSubArchX86_sse1
+           || archinfo_guest->subarch == VexSubArchX86_sse2);
 
    vassert((guest_eip_start >> 32) == 0);
 
@@ -328,7 +328,7 @@ IRBB* bbToIR_X86 ( UChar*           x86code,
          needs to be annulled. */
       size = 0; /* just in case disInstr doesn't set it */
       dres = disInstr( resteerOK, chase_into_ok, 
-                       delta, subarch_guest, &size, &guest_next );
+                       delta, archinfo_guest, &size, &guest_next );
       insn_verbose = False;
 
       /* stay sane ... */
@@ -6997,12 +6997,12 @@ static IRExpr* mk64from16s ( IRTemp t3, IRTemp t2,
    is False, disInstr may not return Dis_Resteer. */
    
 static 
-DisResult disInstr ( /*IN*/  Bool       resteerOK,
-                     /*IN*/  Bool       (*resteerOkFn) ( Addr64 ),
-                     /*IN*/  UInt       delta, 
-                     /*IN*/  VexSubArch subarch,
-                     /*OUT*/ Int*       size,
-                     /*OUT*/ Addr64*    whereNext )
+DisResult disInstr ( /*IN*/  Bool         resteerOK,
+                     /*IN*/  Bool         (*resteerOkFn) ( Addr64 ),
+                     /*IN*/  UInt         delta, 
+                     /*IN*/  VexArchInfo* archinfo,
+                     /*OUT*/ Int*         size,
+                     /*OUT*/ Addr64*      whereNext )
 {
    IRType    ty;
    IRTemp    addr, t0, t1, t2, t3, t4, t5, t6;
@@ -7222,7 +7222,7 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
 
    /* Skip parts of the decoder which don't apply given the stated
       guest subarchitecture. */
-   if (subarch == VexSubArchX86_sse0)
+   if (archinfo->subarch == VexSubArchX86_sse0)
       goto after_sse_decoders;
    
    /* Otherwise we must be doing sse1 or sse2, so we can at least try
@@ -8242,7 +8242,8 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
 
    /* Skip parts of the decoder which don't apply given the stated
       guest subarchitecture. */
-   if (subarch == VexSubArchX86_sse0 || subarch == VexSubArchX86_sse1)
+   if (archinfo->subarch == VexSubArchX86_sse0 
+       || archinfo->subarch == VexSubArchX86_sse1)
       goto after_sse_decoders;
 
    insn = (UChar*)&guest_code[delta];
@@ -11766,7 +11767,7 @@ DisResult disInstr ( /*IN*/  Bool       resteerOK,
          IRDirty* d     = NULL;
          HChar*   fName = NULL;
          void*    fAddr = NULL;
-         switch (subarch) {
+         switch (archinfo->subarch) {
             case VexSubArchX86_sse0:
                fName = "x86g_dirtyhelper_CPUID_sse0";
                fAddr = &x86g_dirtyhelper_CPUID_sse0; 

diff --git a/VEX/priv/host-amd64/hdefs.h b/VEX/priv/host-amd64/hdefs.h
index 9e5d0e21c4a1b14d1816db5e151adddb3af3766d..552e9be47670e139d7e991885b9a5959766730cd 100644 (file)
--- a/VEX/priv/host-amd64/hdefs.h
+++ b/VEX/priv/host-amd64/hdefs.h
@@ -708,7 +708,7 @@ extern Int          emit_AMD64Instr        ( UChar* buf, Int nbuf, AMD64Instr* )
 extern AMD64Instr*  genSpill_AMD64         ( HReg rreg, Int offset );
 extern AMD64Instr*  genReload_AMD64        ( HReg rreg, Int offset );
 extern void         getAllocableRegs_AMD64 ( Int*, HReg** );
-extern HInstrArray* iselBB_AMD64           ( IRBB*, VexSubArch );
+extern HInstrArray* iselBB_AMD64           ( IRBB*, VexArchInfo* );
 
 #endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */
 

diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index 799d7a54ce241b95ff62ba92333496c860263361..9c4ff453648389efc616b851ecd8568003a338f5 100644 (file)
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -3750,11 +3750,12 @@ static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk )
 
 /* Translate an entire BB to amd64 code. */
 
-HInstrArray* iselBB_AMD64 ( IRBB* bb, VexSubArch subarch_host )
+HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArchInfo* archinfo_host )
 {
-   Int      i, j;
-   HReg     hreg, hregHI;
-   ISelEnv* env;
+   Int        i, j;
+   HReg       hreg, hregHI;
+   ISelEnv*   env;
+   VexSubArch subarch_host = archinfo_host->subarch;
 
    /* sanity ... */
    vassert(subarch_host == VexSubArch_NONE);

diff --git a/VEX/priv/host-ppc32/hdefs.h b/VEX/priv/host-ppc32/hdefs.h
index 34b287b28651b3e7ab3937bd8af58420d75fc3a2..0b123fd4910b704d1f1e164c8f0112e70b7e37c2 100644 (file)
--- a/VEX/priv/host-ppc32/hdefs.h
+++ b/VEX/priv/host-ppc32/hdefs.h
@@ -710,7 +710,7 @@ extern Int          emit_PPC32Instr        ( UChar* buf, Int nbuf, PPC32Instr* )
 extern PPC32Instr*  genSpill_PPC32         ( HReg rreg, UShort offsetB );
 extern PPC32Instr*  genReload_PPC32        ( HReg rreg, UShort offsetB );
 extern void         getAllocableRegs_PPC32 ( Int*, HReg** );
-extern HInstrArray* iselBB_PPC32           ( IRBB*, VexSubArch );
+extern HInstrArray* iselBB_PPC32           ( IRBB*, VexArchInfo* );
 
 #endif /* ndef __LIBVEX_HOST_PPC32_HDEFS_H */
 

diff --git a/VEX/priv/host-ppc32/isel.c b/VEX/priv/host-ppc32/isel.c
index 4f30ba764cd174d8c03af0e66aacd50cde1fe2b0..8123a162c9ffa8d93d38a1419ddee25b3bfa76f1 100644 (file)
--- a/VEX/priv/host-ppc32/isel.c
+++ b/VEX/priv/host-ppc32/isel.c
@@ -3529,11 +3529,12 @@ static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk )
 
 /* Translate an entire BB to ppc32 code. */
 
-HInstrArray* iselBB_PPC32 ( IRBB* bb, VexSubArch subarch_host )
+HInstrArray* iselBB_PPC32 ( IRBB* bb, VexArchInfo* archinfo_host )
 {
-   Int      i, j;
-   HReg     hreg, hregHI;
-   ISelEnv* env;
+   Int        i, j;
+   HReg       hreg, hregHI;
+   ISelEnv*   env;
+   VexSubArch subarch_host = archinfo_host->subarch;
 
    /* sanity ... */
    vassert(subarch_host == VexSubArchPPC32_noAV

diff --git a/VEX/priv/host-x86/hdefs.h b/VEX/priv/host-x86/hdefs.h
index 64c5140b5fb6d8788f50f96bb55bcb08a323c7c8..10856f1970b0d70f03a16cb478212e062c3a3e2a 100644 (file)
--- a/VEX/priv/host-x86/hdefs.h
+++ b/VEX/priv/host-x86/hdefs.h
@@ -653,7 +653,7 @@ extern Int          emit_X86Instr        ( UChar* buf, Int nbuf, X86Instr* );
 extern X86Instr*    genSpill_X86         ( HReg rreg, Int offset );
 extern X86Instr*    genReload_X86        ( HReg rreg, Int offset );
 extern void         getAllocableRegs_X86 ( Int*, HReg** );
-extern HInstrArray* iselBB_X86           ( IRBB*, VexSubArch );
+extern HInstrArray* iselBB_X86           ( IRBB*, VexArchInfo* );
 
 #endif /* ndef __LIBVEX_HOST_X86_HDEFS_H */
 

diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c
index 5acca08592bae562bfb73ef20fa798dfd6d67293..0c0766281034c9f46e1ca2c42bf35308a0969f3b 100644 (file)
--- a/VEX/priv/host-x86/isel.c
+++ b/VEX/priv/host-x86/isel.c
@@ -3550,11 +3550,12 @@ static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk )
 
 /* Translate an entire BB to x86 code. */
 
-HInstrArray* iselBB_X86 ( IRBB* bb, VexSubArch subarch_host )
+HInstrArray* iselBB_X86 ( IRBB* bb, VexArchInfo* archinfo_host )
 {
-   Int      i, j;
-   HReg     hreg, hregHI;
-   ISelEnv* env;
+   Int        i, j;
+   HReg       hreg, hregHI;
+   ISelEnv*   env;
+   VexSubArch subarch_host = archinfo_host->subarch;
 
    /* sanity ... */
    vassert(subarch_host == VexSubArchX86_sse0

diff --git a/VEX/priv/main/vex_main.c b/VEX/priv/main/vex_main.c
index 24c618ba59aa1a98933c245480e36a882e47df62..3d345fdbb31b2e3ffc2ab2e5ab1ce4ce5760b2e4 100644 (file)
--- a/VEX/priv/main/vex_main.c
+++ b/VEX/priv/main/vex_main.c
@@ -168,10 +168,10 @@ void LibVEX_Init (
 
 VexTranslateResult LibVEX_Translate (
    /* The instruction sets we are translating from and to. */
-   VexArch    arch_guest,
-   VexSubArch subarch_guest,
-   VexArch    arch_host,
-   VexSubArch subarch_host,
+   VexArch      arch_guest,
+   VexArchInfo* archinfo_guest,
+   VexArch      arch_host,
+   VexArchInfo* archinfo_host,
    /* IN: the block to translate, and its guest address. */
    UChar*  guest_bytes,
    Addr64  guest_bytes_addr,
@@ -207,12 +207,12 @@ VexTranslateResult LibVEX_Translate (
    HInstr*      (*genReload)   ( HReg, Int );
    void         (*ppInstr)     ( HInstr* );
    void         (*ppReg)       ( HReg );
-   HInstrArray* (*iselBB)      ( IRBB*, VexSubArch );
+   HInstrArray* (*iselBB)      ( IRBB*, VexArchInfo* );
    IRBB*        (*bbToIR)      ( UChar*, Addr64, 
                                  VexGuestExtents*, 
                                  Bool(*)(Addr64), 
                                  Bool(*)(Addr64), 
-                                 Bool, VexSubArch );
+                                 Bool, VexArchInfo* );
    Int          (*emit)        ( UChar*, Int, HInstr* );
    IRExpr*      (*specHelper)  ( HChar*, IRExpr** );
    Bool         (*preciseMemExnsFn) ( Int, Int );
@@ -270,9 +270,9 @@ VexTranslateResult LibVEX_Translate (
          emit        = (Int(*)(UChar*,Int,HInstr*)) emit_X86Instr;
          host_is_bigendian = False;
          host_word_type    = Ity_I32;
-         vassert(subarch_host == VexSubArchX86_sse0
-                 || subarch_host == VexSubArchX86_sse1
-                 || subarch_host == VexSubArchX86_sse2);
+         vassert(archinfo_host->subarch == VexSubArchX86_sse0
+                 || archinfo_host->subarch == VexSubArchX86_sse1
+                 || archinfo_host->subarch == VexSubArchX86_sse2);
          break;
 
       case VexArchAMD64:
@@ -289,7 +289,7 @@ VexTranslateResult LibVEX_Translate (
          emit        = (Int(*)(UChar*,Int,HInstr*)) emit_AMD64Instr;
          host_is_bigendian = False;
          host_word_type    = Ity_I64;
-         vassert(subarch_host == VexSubArch_NONE);
+         vassert(archinfo_host->subarch == VexSubArch_NONE);
          break;
 
       case VexArchPPC32:
@@ -306,8 +306,8 @@ VexTranslateResult LibVEX_Translate (
          emit        = (Int(*)(UChar*,Int,HInstr*)) emit_PPC32Instr;
          host_is_bigendian = True;
          host_word_type    = Ity_I32;
-         vassert(subarch_guest == VexSubArchPPC32_noAV
-                 || subarch_guest == VexSubArchPPC32_AV);
+         vassert(archinfo_guest->subarch == VexSubArchPPC32_noAV
+                 || archinfo_guest->subarch == VexSubArchPPC32_AV);
          break;
 
       default:
@@ -324,9 +324,9 @@ VexTranslateResult LibVEX_Translate (
          guest_sizeB      = sizeof(VexGuestX86State);
          guest_word_type  = Ity_I32;
          guest_layout     = &x86guest_layout;
-         vassert(subarch_guest == VexSubArchX86_sse0
-                 || subarch_guest == VexSubArchX86_sse1
-                 || subarch_guest == VexSubArchX86_sse2);
+         vassert(archinfo_guest->subarch == VexSubArchX86_sse0
+                 || archinfo_guest->subarch == VexSubArchX86_sse1
+                 || archinfo_guest->subarch == VexSubArchX86_sse2);
          break;
 
       case VexArchAMD64:
@@ -336,7 +336,7 @@ VexTranslateResult LibVEX_Translate (
          guest_sizeB      = sizeof(VexGuestAMD64State);
          guest_word_type  = Ity_I64;
          guest_layout     = &amd64guest_layout;
-         vassert(subarch_guest == VexSubArch_NONE);
+         vassert(archinfo_guest->subarch == VexSubArch_NONE);
          break;
 
       case VexArchARM:
@@ -346,7 +346,7 @@ VexTranslateResult LibVEX_Translate (
          guest_sizeB      = sizeof(VexGuestARMState);
          guest_word_type  = Ity_I32;
          guest_layout     = &armGuest_layout;
-         vassert(subarch_guest == VexSubArchARM_v4);
+         vassert(archinfo_guest->subarch == VexSubArchARM_v4);
          break;
 
       case VexArchPPC32:
@@ -356,8 +356,8 @@ VexTranslateResult LibVEX_Translate (
          guest_sizeB      = sizeof(VexGuestPPC32State);
          guest_word_type  = Ity_I32;
          guest_layout     = &ppc32Guest_layout;
-         vassert(subarch_guest == VexSubArchPPC32_noAV
-                 || subarch_guest == VexSubArchPPC32_AV);
+         vassert(archinfo_guest->subarch == VexSubArchPPC32_noAV
+                 || archinfo_guest->subarch == VexSubArchPPC32_AV);
          break;
 
       default:
@@ -369,7 +369,7 @@ VexTranslateResult LibVEX_Translate (
       /* doesn't necessarily have to be true, but if it isn't it means
          we are simulating one flavour of an architecture a different
          flavour of the same architecture, which is pretty strange. */
-      vassert(subarch_guest == subarch_host);
+      vassert(archinfo_guest->subarch == archinfo_host->subarch);
    }
 
    if (vex_traceflags & VEX_TRACE_FE)
@@ -383,7 +383,7 @@ VexTranslateResult LibVEX_Translate (
                    byte_accessible,
                    chase_into_ok,
                    host_is_bigendian,
-                   subarch_guest );
+                   archinfo_guest );
 
    if (irbb == NULL) {
       /* Access failure. */
@@ -489,7 +489,7 @@ VexTranslateResult LibVEX_Translate (
                    " Instruction selection "
                    "------------------------\n");
 
-   vcode = iselBB ( irbb, subarch_host );
+   vcode = iselBB ( irbb, archinfo_host );
 
    if (vex_traceflags & VEX_TRACE_VCODE)
       vex_printf("\n");
@@ -592,7 +592,7 @@ HChar* LibVEX_EmWarn_string ( VexEmWarn ew )
    }
 }
 
-/* --------- Arch/Subarch names. --------- */
+/* --------- Arch/Subarch stuff. --------- */
 
 const HChar* LibVEX_ppVexArch ( VexArch arch )
 {
@@ -621,6 +621,14 @@ const HChar* LibVEX_ppVexSubArch ( VexSubArch subarch )
    }
 }
 
+/* Write default settings info *vai. */
+void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai )
+{
+   vai->subarch              = VexSubArch_INVALID;
+   vai->ppc32_cache_line_szB = 0;
+}
+
+
 /*---------------------------------------------------------------*/
 /*--- end                                     main/vex_main.c ---*/
 /*---------------------------------------------------------------*/

diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index 57ba6ec8dbc28aa179c0fdfaa773d821e4ae562d..871da1aad3694314c02320819c9b351d0c9172d4 100644 (file)
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -46,7 +46,7 @@
 /*---------------------------------------------------------------*/
 
 /*-------------------------------------------------------*/
-/*--- Architectures and architecture variants         ---*/
+/*--- Architectures, variants, and other arch info    ---*/
 /*-------------------------------------------------------*/
 
 typedef 
@@ -78,6 +78,24 @@ extern const HChar* LibVEX_ppVexArch    ( VexArch );
 extern const HChar* LibVEX_ppVexSubArch ( VexSubArch );
 
 
+/* This struct is a bit of a hack, but is needed to carry misc
+   important bits of info about an arch.  Fields which are optional or
+   ignored on some arch should be set to zero. */
+
+typedef
+   struct {
+      /* This is the only mandatory field. */
+      VexSubArch subarch;
+      /* PPC32 only: size of cache line */
+      Int ppc32_cache_line_szB;
+   }
+   VexArchInfo;
+
+/* Write default settings info *vai. */
+extern 
+void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai );
+
+
 /*-------------------------------------------------------*/
 /*--- Control of Vex's optimiser (iropt).             ---*/
 /*-------------------------------------------------------*/
@@ -247,10 +265,10 @@ typedef
 extern 
 VexTranslateResult LibVEX_Translate (
    /* The instruction sets we are translating from and to. */
-   VexArch    arch_guest,
-   VexSubArch subarch_guest,
-   VexArch    arch_host,
-   VexSubArch subarch_host,
+   VexArch      arch_guest,
+   VexArchInfo* archinfo_guest,
+   VexArch      arch_host,
+   VexArchInfo* archinfo_host,
    /* IN: the block to translate, and its guest address. */
    UChar*  guest_bytes,
    Addr64  guest_bytes_addr,