LoongArch: Define hook TARGET_COMPUTE_PRESSURE_CLASSES[PR120476].

The rtx cost value defined by the target backend affects the
calculation of register pressure classes in the IRA, thus affecting
scheduling.  This may cause program performance degradation.
For example, OpenSSL 3.5.1 SHA512 and SPEC CPU 2017 exchange_r.

This problem can be avoided by defining a set of register pressure
classes in the target backend instead of using the default IRA to
automatically calculate them.

gcc/ChangeLog:

	PR target/120476
	* config/loongarch/loongarch.cc
	(loongarch_compute_pressure_classes): New function.
	(TARGET_COMPUTE_PRESSURE_CLASSES): Define.

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index b169d2ffcd06156a52a54e9d757df75cd8d37196..3b62ed9cfb9f60b7b7f847a4d230679b7dd3e035 100644 (file)
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -11182,6 +11182,18 @@ loongarch_bitint_type_info (int n, struct bitint_info *info)
   return true;
 }
 
+/* Implement TARGET_COMPUTE_PRESSURE_CLASSES.  */
+
+static int
+loongarch_compute_pressure_classes (reg_class *classes)
+{
+  int i = 0;
+  classes[i++] = GENERAL_REGS;
+  classes[i++] = FP_REGS;
+  classes[i++] = FCC_REGS;
+  return i;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -11459,6 +11471,9 @@ loongarch_bitint_type_info (int n, struct bitint_info *info)
 #undef TARGET_C_BITINT_TYPE_INFO
 #define TARGET_C_BITINT_TYPE_INFO loongarch_bitint_type_info
 
+#undef TARGET_COMPUTE_PRESSURE_CLASSES
+#define TARGET_COMPUTE_PRESSURE_CLASSES loongarch_compute_pressure_classes
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-loongarch.h"