3.8-stable patches

added patches:
	arm-7635-1-versatile-fix-the-pci-irq-regression.patch

diff --git a/queue-3.8/arm-7635-1-versatile-fix-the-pci-irq-regression.patch b/queue-3.8/arm-7635-1-versatile-fix-the-pci-irq-regression.patch
new file mode 100644 (file)
index 0000000..dfc386c
--- /dev/null
+++ b/queue-3.8/arm-7635-1-versatile-fix-the-pci-irq-regression.patch
@@ -0,0 +1,116 @@
+From e3e92a7be6936dff1de80e66b0b683d54e9e02d8 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 28 Jan 2013 21:58:22 +0100
+Subject: ARM: 7635/1: versatile: fix the PCI IRQ regression
+
+From: Linus Walleij <linus.walleij@linaro.org>
+
+commit e3e92a7be6936dff1de80e66b0b683d54e9e02d8 upstream.
+
+The PCI IRQs were regressing due to two things:
+
+- The PCI glue layer was using an hard-coded IRQ 27 offset.
+  This caused the immediate regression.
+
+- The SIC IRQ mask was inverted (i.e. a bit was indeed set to
+  one for each valid IRQ on the SIC, but accidentally inverted
+  in the init call). This has been around forever, but we have
+  been saved by some other forgiving code that would reserve
+  IRQ descriptors in this range, as the versatile is
+  non-sparse.
+
+When the IRQs were bumped up 32 steps so as to avoid using IRQ
+zero and avoid touching the 16 legacy IRQs, things broke.
+
+Introduce an explicit valid mask for the IRQs that are active
+on the PIC/SIC, and pass that. Use the BIT() macro from
+<linux/bitops.h> to make sure we hit the right bits, readily
+defined in <mach/platform.h>.
+
+Reported-by: Tetsuo Handa <penguin-kernel@i-love.sakura.ne.jp>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-versatile/core.c |   15 ++++++++++++++-
+ arch/arm/mach-versatile/pci.c  |   11 ++++++-----
+ 2 files changed, 20 insertions(+), 6 deletions(-)
+
+--- a/arch/arm/mach-versatile/core.c
++++ b/arch/arm/mach-versatile/core.c
+@@ -36,6 +36,7 @@
+ #include <linux/gfp.h>
+ #include <linux/clkdev.h>
+ #include <linux/mtd/physmap.h>
++#include <linux/bitops.h>
+ 
+ #include <asm/irq.h>
+ #include <asm/hardware/arm_timer.h>
+@@ -65,16 +66,28 @@
+ #define VA_VIC_BASE           __io_address(VERSATILE_VIC_BASE)
+ #define VA_SIC_BASE           __io_address(VERSATILE_SIC_BASE)
+ 
++/* These PIC IRQs are valid in each configuration */
++#define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
++                      BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
++                      BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
++                      BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
++                      BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
++                      BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
++                      BIT(SIC_INT_PCI3)
+ #if 1
+ #define IRQ_MMCI0A    IRQ_VICSOURCE22
+ #define IRQ_AACI      IRQ_VICSOURCE24
+ #define IRQ_ETH               IRQ_VICSOURCE25
+ #define PIC_MASK      0xFFD00000
++#define PIC_VALID     PIC_VALID_ALL
+ #else
+ #define IRQ_MMCI0A    IRQ_SIC_MMCI0A
+ #define IRQ_AACI      IRQ_SIC_AACI
+ #define IRQ_ETH               IRQ_SIC_ETH
+ #define PIC_MASK      0
++#define PIC_VALID     PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
++                      BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
++                      BIT(SIC_INT_ETH)
+ #endif
+ 
+ /* Lookup table for finding a DT node that represents the vic instance */
+@@ -102,7 +115,7 @@ void __init versatile_init_irq(void)
+                                             VERSATILE_SIC_BASE);
+ 
+       fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
+-              IRQ_VICSOURCE31, ~PIC_MASK, np);
++              IRQ_VICSOURCE31, PIC_VALID, np);
+ 
+       /*
+        * Interrupts on secondary controller from 0 to 8 are routed to
+--- a/arch/arm/mach-versatile/pci.c
++++ b/arch/arm/mach-versatile/pci.c
+@@ -23,6 +23,7 @@
+ #include <linux/io.h>
+ 
+ #include <mach/hardware.h>
++#include <mach/irqs.h>
+ #include <asm/irq.h>
+ #include <asm/mach/pci.h>
+ 
+@@ -327,12 +328,12 @@ static int __init versatile_map_irq(cons
+       int irq;
+ 
+       /* slot,  pin,  irq
+-       *  24     1     27
+-       *  25     1     28
+-       *  26     1     29
+-       *  27     1     30
++       *  24     1     IRQ_SIC_PCI0
++       *  25     1     IRQ_SIC_PCI1
++       *  26     1     IRQ_SIC_PCI2
++       *  27     1     IRQ_SIC_PCI3
+        */
+-      irq = 27 + ((slot - 24 + pin - 1) & 3);
++      irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3);
+ 
+       return irq;
+ }

diff --git a/queue-3.8/series b/queue-3.8/series
index 1eb2f4de99a2618f72a14a98fa688e7e80c9a763..e83ab369f834c5b3340d3282e26f723028abdd74 100644 (file)
--- a/queue-3.8/series
+++ b/queue-3.8/series
@@ -98,3 +98,4 @@ staging-vt6656-revert-64bit-fixes-dpc.c-incorrect-addressing-of-void-structure.p
 staging-vt6656-fix-urb-submitted-while-active-warning.patch
 asoc-wm2200-correct-in2l-and-in3l-digital-mute.patch
 asoc-arizona-fixed-a-bug-in-fll-fractional-calculation.patch
+arm-7635-1-versatile-fix-the-pci-irq-regression.patch