arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b

Enable PCIe2_0 controller and its voltage supply, which is routed
to the M.2 E-Key on the upper side of the Radxa Rock 5B.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230918141451.131247-4-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 6e52b5cf49a943083051bd7cefde594135441f71..947a5ebe5bb3ca6b44caf68d43d46c54492e2882 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -44,6 +44,21 @@
                #cooling-cells = <2>;
        };
 
+       vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+               regulator-name = "vcc3v3_pcie2x1l0";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               startup-delay-us = <50000>;
+               vin-supply = <&vcc5v0_sys>;
+       };
+
        vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
                compatible = "regulator-fixed";
                regulator-name = "vcc3v3_pcie2x1l2";
@@ -104,6 +119,10 @@
        status = "okay";
 };
 
+&combphy1_ps {
+       status = "okay";
+};
+
 &cpu_b0 {
        cpu-supply = <&vdd_cpu_big0_s0>;
 };
@@ -230,6 +249,14 @@
        };
 };
 
+&pcie2x1l0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_0_rst>;
+       reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+       vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+       status = "okay";
+};
+
 &pcie2x1l2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie2_2_rst>;
@@ -264,6 +291,14 @@
        };
 
        pcie2 {
+               pcie2_0_rst: pcie2-0-rst {
+                       rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
+                       rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
                pcie2_2_rst: pcie2-2-rst {
                        rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
                };