aarch64: Treat operand ADDR_SIMPLE as address with base register

The AArch64 instruction table (aarch64-tbl.h) defines the operand
ADDR_SIMPLE as "address with base register (no offset)". During assembly
it is correctly encoded as address with base register (addr.base_regno)
in parse_operands. In warn_unpredictable_ldst it is erroneously treated
as register number (reg.regno).

This resolves the assembler test case "Diagnostics Quality" to
erroneously fail when changing the union in struct aarch64_opnd_info
from union to struct for debugging purposes.

gas/
	* config/tc-aarch64.c: Treat operand ADDR_SIMPLE as address with
	base register.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ad4dd57617460e7b23cf153e7cac2015dc7362f3..5d15ee9fc029e4ad211ecd7ce27aee6817824b86 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8509,7 +8509,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
                  (_("unpredictable: identical transfer and status registers"
                     " --`%s'"),str);
 
-             if (opnds[0].reg.regno == opnds[2].reg.regno)
+             if (opnds[0].reg.regno == opnds[2].addr.base_regno)
                {
                  if (!(opcode->opcode & (1 << 21)))
                    /*  Store-Exclusive is unpredictable if Rn == Rs.  */
@@ -8526,8 +8526,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
 
              /* Store-Exclusive pair is unpredictable if Rn == Rs.  */
              if ((opcode->opcode & (1 << 21))
-                 && opnds[0].reg.regno == opnds[3].reg.regno
-                 && opnds[3].reg.regno != REG_SP)
+                 && opnds[0].reg.regno == opnds[3].addr.base_regno
+                 && opnds[3].addr.base_regno != REG_SP)
                as_warn (_("unpredictable: identical base and status registers"
                           " --`%s'"),str);
            }