Added 'Bool mode64' to the various backend functions, to distinguish 32/64bit arch's.

This will be needed for the ppc32/64 backend.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1487

diff --git a/VEX/priv/guest-generic/bb_to_IR.c b/VEX/priv/guest-generic/bb_to_IR.c
index 249fb3f861d734243adbe78c6ea9d2c5bfa78837..cc3df974fc4fad8ac3b5dbee28897f1b6ce78bce 100644 (file)
--- a/VEX/priv/guest-generic/bb_to_IR.c
+++ b/VEX/priv/guest-generic/bb_to_IR.c
@@ -274,8 +274,8 @@ IRBB* bb_to_IR ( /*OUT*/VexGuestExtents* vge,
             vassert(resteerOKfn(dres.continueAt));
             delta = dres.continueAt - guest_IP_bbstart;
             /* we now have to start a new extent slot. */
-           vge->n_used++;
-           vassert(vge->n_used <= 3);
+            vge->n_used++;
+            vassert(vge->n_used <= 3);
             vge->base[vge->n_used-1] = dres.continueAt;
             vge->len[vge->n_used-1] = 0;
             n_resteers++;

diff --git a/VEX/priv/host-amd64/hdefs.c b/VEX/priv/host-amd64/hdefs.c
index 3ba3472cdccb8fa7e7991cceca8e722f72137d5a..5589bc807c0fbc4f984393d91558a481f1675c13 100644 (file)
--- a/VEX/priv/host-amd64/hdefs.c
+++ b/VEX/priv/host-amd64/hdefs.c
@@ -1019,8 +1019,9 @@ AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ) {
    return i;
 }
 
-void ppAMD64Instr ( AMD64Instr* i ) 
+void ppAMD64Instr ( AMD64Instr* i, Bool mode64 ) 
 {
+   vassert(mode64 == True);
    switch (i->tag) {
       case Ain_Imm64: 
          vex_printf("movabsq $0x%llx,", i->Ain.Imm64.imm64);
@@ -1335,9 +1336,10 @@ void ppAMD64Instr ( AMD64Instr* i )
 
 /* --------- Helpers for register allocation. --------- */
 
-void getRegUsage_AMD64Instr ( HRegUsage* u, AMD64Instr* i )
+void getRegUsage_AMD64Instr ( HRegUsage* u, AMD64Instr* i, Bool mode64 )
 {
    Bool unary;
+   vassert(mode64 == True);
    initHRegUsage(u);
    switch (i->tag) {
       case Ain_Imm64:
@@ -1607,7 +1609,7 @@ void getRegUsage_AMD64Instr ( HRegUsage* u, AMD64Instr* i )
          addHRegUse(u, HRmWrite, i->Ain.SseShuf.dst);
          return;
       default:
-         ppAMD64Instr(i);
+         ppAMD64Instr(i, mode64);
          vpanic("getRegUsage_AMD64Instr");
    }
 }
@@ -1618,8 +1620,9 @@ static inline void mapReg(HRegRemap* m, HReg* r)
    *r = lookupHRegRemap(m, *r);
 }
 
-void mapRegs_AMD64Instr ( HRegRemap* m, AMD64Instr* i )
+void mapRegs_AMD64Instr ( HRegRemap* m, AMD64Instr* i, Bool mode64 )
 {
+   vassert(mode64 == True);
    switch (i->tag) {
       case Ain_Imm64:
          mapReg(m, &i->Ain.Imm64.dst);
@@ -1781,7 +1784,7 @@ void mapRegs_AMD64Instr ( HRegRemap* m, AMD64Instr* i )
          mapReg(m, &i->Ain.SseShuf.dst);
          return;
       default:
-         ppAMD64Instr(i);
+         ppAMD64Instr(i, mode64);
          vpanic("mapRegs_AMD64Instr");
    }
 }
@@ -1818,11 +1821,12 @@ Bool isMove_AMD64Instr ( AMD64Instr* i, HReg* src, HReg* dst )
    register allocator.  Note it's critical these don't write the
    condition codes. */
 
-AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offsetB )
+AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offsetB, Bool mode64 )
 {
    AMD64AMode* am;
    vassert(offsetB >= 0);
    vassert(!hregIsVirtual(rreg));
+   vassert(mode64 == True);
    am = AMD64AMode_IR(offsetB, hregAMD64_RBP());
 
    switch (hregClass(rreg)) {
@@ -1836,11 +1840,12 @@ AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offsetB )
    }
 }
 
-AMD64Instr* genReload_AMD64 ( HReg rreg, Int offsetB )
+AMD64Instr* genReload_AMD64 ( HReg rreg, Int offsetB, Bool mode64 )
 {
    AMD64AMode* am;
    vassert(offsetB >= 0);
    vassert(!hregIsVirtual(rreg));
+   vassert(mode64 == True);
    am = AMD64AMode_IR(offsetB, hregAMD64_RBP());
    switch (hregClass(rreg)) {
       case HRcInt64:
@@ -2195,7 +2200,7 @@ static UChar* do_ffree_st ( UChar* p, Int n )
    Note that buf is not the insn's final place, and therefore it is
    imperative to emit position-independent code. */
 
-Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i )
+Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i, Bool mode64 )
 {
    UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc;
    UInt   xtra;
@@ -2205,13 +2210,14 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i )
    UChar* ptmp;
    Int    j;
    vassert(nbuf >= 32);
+   vassert(mode64 == True);
 
    /* Wrap an integer as a int register, for use assembling
       GrpN insns, in which the greg field is used as a sub-opcode
       and does not really contain a register. */
 #  define fake(_n) mkHReg((_n), HRcInt64, False)
 
-   /* vex_printf("asm  "); ppAMD64Instr(i); vex_printf("\n"); */
+   /* vex_printf("asm  "); ppAMD64Instr(i, mode64); vex_printf("\n"); */
 
    switch (i->tag) {
 
@@ -3337,7 +3343,7 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i )
    }
 
   bad:
-   ppAMD64Instr(i);
+   ppAMD64Instr(i, mode64);
    vpanic("emit_AMD64Instr");
    /*NOTREACHED*/
    

diff --git a/VEX/priv/host-amd64/hdefs.h b/VEX/priv/host-amd64/hdefs.h
index 46a376a63507256f967efaa5ef3ba45040baf300..b7a05804fb5a1678d850808226d92d260d794ae7 100644 (file)
--- a/VEX/priv/host-amd64/hdefs.h
+++ b/VEX/priv/host-amd64/hdefs.h
@@ -708,16 +708,16 @@ extern AMD64Instr* AMD64Instr_SseCMov    ( AMD64CondCode, HReg src, HReg dst );
 extern AMD64Instr* AMD64Instr_SseShuf    ( Int order, HReg src, HReg dst );
 
 
-extern void ppAMD64Instr ( AMD64Instr* );
+extern void ppAMD64Instr ( AMD64Instr*, Bool );
 
 /* Some functions that insulate the register allocator from details
    of the underlying instruction set. */
-extern void         getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr* );
-extern void         mapRegs_AMD64Instr     ( HRegRemap*, AMD64Instr* );
+extern void         getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr*, Bool );
+extern void         mapRegs_AMD64Instr     ( HRegRemap*, AMD64Instr*, Bool );
 extern Bool         isMove_AMD64Instr      ( AMD64Instr*, HReg*, HReg* );
-extern Int          emit_AMD64Instr        ( UChar* buf, Int nbuf, AMD64Instr* );
-extern AMD64Instr*  genSpill_AMD64         ( HReg rreg, Int offset );
-extern AMD64Instr*  genReload_AMD64        ( HReg rreg, Int offset );
+extern Int          emit_AMD64Instr        ( UChar* buf, Int nbuf, AMD64Instr*, Bool );
+extern AMD64Instr*  genSpill_AMD64         ( HReg rreg, Int offset, Bool );
+extern AMD64Instr*  genReload_AMD64        ( HReg rreg, Int offset, Bool );
 extern void         getAllocableRegs_AMD64 ( Int*, HReg** );
 extern HInstrArray* iselBB_AMD64           ( IRBB*, VexArchInfo* );
 

diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index 58548886ab225e90efcbca53a6a5b9ca776fe4bc..71e9b34ceb0d8cfeac42a026e8dc6ef2abf04020 100644 (file)
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -171,7 +171,7 @@ static void addInstr ( ISelEnv* env, AMD64Instr* instr )
 {
    addHInstr(env->code, instr);
    if (vex_traceflags & VEX_TRACE_VCODE) {
-      ppAMD64Instr(instr);
+      ppAMD64Instr(instr, False);
       vex_printf("\n");
    }
 }

diff --git a/VEX/priv/host-generic/h_generic_regs.h b/VEX/priv/host-generic/h_generic_regs.h
index d1535e6d33255e97c28e7471855c53c0601609cf..b1ece43414e06f3f008b7e9ea3868e536d41097d 100644 (file)
--- a/VEX/priv/host-generic/h_generic_regs.h
+++ b/VEX/priv/host-generic/h_generic_regs.h
@@ -253,20 +253,23 @@ HInstrArray* doRegisterAllocation (
    Bool (*isMove) (HInstr*, HReg*, HReg*),
 
    /* Get info about register usage in this insn. */
-   void (*getRegUsage) (HRegUsage*, HInstr*),
+   void (*getRegUsage) (HRegUsage*, HInstr*, Bool),
 
    /* Apply a reg-reg mapping to an insn. */
-   void (*mapRegs) (HRegRemap*, HInstr*),
+   void (*mapRegs) (HRegRemap*, HInstr*, Bool),
 
    /* Return an insn to spill/restore a real reg to a spill slot
       offset. */
-   HInstr* (*genSpill) ( HReg, Int ),
-   HInstr* (*genReload) ( HReg, Int ),
+   HInstr* (*genSpill) ( HReg, Int, Bool ),
+   HInstr* (*genReload) ( HReg, Int, Bool ),
    Int     guest_sizeB,
 
    /* For debug printing only. */
-   void (*ppInstr) ( HInstr* ),
-   void (*ppReg) ( HReg )
+   void (*ppInstr) ( HInstr*, Bool ),
+   void (*ppReg) ( HReg ),
+
+   /* 32/64bit mode */
+   Bool mode64
 );
 
 

diff --git a/VEX/priv/host-generic/reg_alloc2.c b/VEX/priv/host-generic/reg_alloc2.c
index 1d6b631d54909e6bee65becc19beb307e502e073..6e4f1873efa7287db5eed829045e5ab130cd99f2 100644 (file)
--- a/VEX/priv/host-generic/reg_alloc2.c
+++ b/VEX/priv/host-generic/reg_alloc2.c
@@ -155,14 +155,15 @@ typedef
 
 /* Does this instruction mention a particular reg? */
 static Bool instrMentionsReg ( 
-   void (*getRegUsage) (HRegUsage*, HInstr*),
+   void (*getRegUsage) (HRegUsage*, HInstr*, Bool),
    HInstr* instr, 
-   HReg r 
+   HReg r,
+   Bool mode64
 )
 {
    Int       i;
    HRegUsage reg_usage;
-   (*getRegUsage)(&reg_usage, instr);
+   (*getRegUsage)(&reg_usage, instr, mode64);
    for (i = 0; i < reg_usage.n_used; i++)
       if (reg_usage.hreg[i] == r)
          return True;
@@ -184,11 +185,12 @@ static Bool instrMentionsReg (
    spill, or -1 if none was found.  */
 static
 Int findMostDistantlyMentionedVReg ( 
-   void (*getRegUsage) (HRegUsage*, HInstr*),
+   void (*getRegUsage) (HRegUsage*, HInstr*, Bool),
    HInstrArray* instrs_in,
    Int          search_from_instr,
    RRegState*   state,
-   Int          n_state
+   Int          n_state,
+   Bool         mode64
 )
 {
    Int k, m;
@@ -201,7 +203,7 @@ Int findMostDistantlyMentionedVReg (
       vassert(state[k].disp == Bound);
       for (m = search_from_instr; m < instrs_in->arr_used; m++) {
          if (instrMentionsReg(getRegUsage, 
-                              instrs_in->arr[m], state[k].vreg))
+                              instrs_in->arr[m], state[k].vreg, mode64))
             break;
       }
       if (m > furthest) {
@@ -258,23 +260,26 @@ HInstrArray* doRegisterAllocation (
 
    /* Return True iff the given insn is a reg-reg move, in which
       case also return the src and dst regs. */
-   Bool (*isMove) (HInstr*, HReg*, HReg*),
+   Bool (*isMove) ( HInstr*, HReg*, HReg* ),
 
    /* Get info about register usage in this insn. */
-   void (*getRegUsage) (HRegUsage*, HInstr*),
+   void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ),
 
    /* Apply a reg-reg mapping to an insn. */
-   void (*mapRegs) (HRegRemap*, HInstr*),
+   void (*mapRegs) ( HRegRemap*, HInstr*, Bool ),
 
    /* Return an insn to spill/restore a real reg to a spill slot
       byte offset. */
-   HInstr* (*genSpill) ( HReg, Int ),
-   HInstr* (*genReload) ( HReg, Int ),
+   HInstr* (*genSpill) ( HReg, Int, Bool ),
+   HInstr* (*genReload) ( HReg, Int, Bool ),
    Int     guest_sizeB,
 
    /* For debug printing only. */
-   void (*ppInstr) ( HInstr* ),
-   void (*ppReg) ( HReg )
+   void (*ppInstr) ( HInstr*, Bool ),
+   void (*ppReg) ( HReg ),
+
+   /* 32/64bit mode */
+   Bool mode64
 )
 {
 #  define N_SPILL64S  (LibVEX_N_SPILL_BYTES / 8)
@@ -336,7 +341,7 @@ HInstrArray* doRegisterAllocation (
         HInstr* _tmp = (_instr);              \
         if (DEBUG_REGALLOC) {                 \
            vex_printf("**  ");                \
-           (*ppInstr)(_tmp);                  \
+           (*ppInstr)(_tmp, mode64);          \
            vex_printf("\n\n");                \
         }                                     \
         addHInstr ( instrs_out, _tmp );       \
@@ -451,11 +456,11 @@ HInstrArray* doRegisterAllocation (
 
    for (ii = 0; ii < instrs_in->arr_used; ii++) {
 
-      (*getRegUsage)( &reg_usage, instrs_in->arr[ii] );
+      (*getRegUsage)( &reg_usage, instrs_in->arr[ii], mode64 );
 
 #     if 0
       vex_printf("\n%d  stage1: ", ii);
-      (*ppInstr)(instrs_in->arr[ii]);
+      (*ppInstr)(instrs_in->arr[ii], mode64);
       vex_printf("\n");
       ppHRegUsage(&reg_usage);
 #     endif
@@ -472,7 +477,7 @@ HInstrArray* doRegisterAllocation (
          k = hregNumber(vreg);
          if (k < 0 || k >= n_vregs) {
             vex_printf("\n");
-            (*ppInstr)(instrs_in->arr[ii]);
+            (*ppInstr)(instrs_in->arr[ii], mode64);
             vex_printf("\n");
             vex_printf("vreg %d, n_vregs %d\n", k, n_vregs);
             vpanic("doRegisterAllocation: out-of-range vreg");
@@ -561,7 +566,7 @@ HInstrArray* doRegisterAllocation (
                   (*ppReg)(available_real_regs[k]);
                   vex_printf("\n");
                   vex_printf("\nOFFENDING instr = ");
-                  (*ppInstr)(instrs_in->arr[ii]);
+                  (*ppInstr)(instrs_in->arr[ii], mode64);
                   vex_printf("\n");
                   vpanic("doRegisterAllocation: "
                          "first event for rreg is Read");
@@ -574,7 +579,7 @@ HInstrArray* doRegisterAllocation (
                   (*ppReg)(available_real_regs[k]);
                   vex_printf("\n");
                   vex_printf("\nOFFENDING instr = ");
-                  (*ppInstr)(instrs_in->arr[ii]);
+                  (*ppInstr)(instrs_in->arr[ii], mode64);
                   vex_printf("\n");
                   vpanic("doRegisterAllocation: "
                          "first event for rreg is Modify");
@@ -786,7 +791,7 @@ HInstrArray* doRegisterAllocation (
 #     if DEBUG_REGALLOC
       vex_printf("\n====----====---- Insn %d ----====----====\n", ii);
       vex_printf("---- ");
-      (*ppInstr)(instrs_in->arr[ii]);
+      (*ppInstr)(instrs_in->arr[ii], mode64);
       vex_printf("\n\nInitial state:\n");
       PRINT_STATE;
       vex_printf("\n");
@@ -1009,7 +1014,8 @@ HInstrArray* doRegisterAllocation (
                if (vreg_lrs[m].dead_before > ii) {
                   vassert(vreg_lrs[m].reg_class != HRcINVALID);
                   EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
-                                           vreg_lrs[m].spill_offset ) );
+                                           vreg_lrs[m].spill_offset,
+                                           mode64 ) );
                }
             }
             rreg_state[k].disp = Unavail;
@@ -1033,7 +1039,7 @@ HInstrArray* doRegisterAllocation (
          We also build up the final vreg->rreg mapping to be applied
          to the insn. */
       
-      (*getRegUsage)( &reg_usage, instrs_in->arr[ii] );
+      (*getRegUsage)( &reg_usage, instrs_in->arr[ii], mode64 );
 
       initHRegRemap(&remap);
 
@@ -1098,7 +1104,8 @@ HInstrArray* doRegisterAllocation (
             if (reg_usage.mode[j] != HRmWrite) {
                vassert(vreg_lrs[m].reg_class != HRcINVALID);
                EMIT_INSTR( (*genReload)( rreg_state[k].rreg,
-                                         vreg_lrs[m].spill_offset ) );
+                                         vreg_lrs[m].spill_offset,
+                                         mode64 ) );
             }
             continue;
          }
@@ -1133,7 +1140,7 @@ HInstrArray* doRegisterAllocation (
             of consequent reloads required. */
          spillee
             = findMostDistantlyMentionedVReg ( 
-                 getRegUsage, instrs_in, ii+1, rreg_state, n_rregs );
+                 getRegUsage, instrs_in, ii+1, rreg_state, n_rregs, mode64 );
 
          if (spillee == -1) {
             /* Hmmmmm.  There don't appear to be any spill candidates.
@@ -1161,7 +1168,8 @@ HInstrArray* doRegisterAllocation (
          vassert(vreg_lrs[m].dead_before > ii);
          vassert(vreg_lrs[m].reg_class != HRcINVALID);
          EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg,
-                                  vreg_lrs[m].spill_offset ) );
+                                  vreg_lrs[m].spill_offset,
+                                  mode64 ) );
 
          /* Update the rreg_state to reflect the new assignment for this
             rreg. */
@@ -1177,7 +1185,8 @@ HInstrArray* doRegisterAllocation (
          if (reg_usage.mode[j] != HRmWrite) {
             vassert(vreg_lrs[m].reg_class != HRcINVALID);
             EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg,
-                                      vreg_lrs[m].spill_offset ) );
+                                      vreg_lrs[m].spill_offset,
+                                      mode64 ) );
          }
 
          /* So after much twisting and turning, we have vreg mapped to
@@ -1198,7 +1207,7 @@ HInstrArray* doRegisterAllocation (
       */
 
       /* NOTE, DESTRUCTIVELY MODIFIES instrs_in->arr[ii]. */
-      (*mapRegs)( &remap, instrs_in->arr[ii] );
+      (*mapRegs)( &remap, instrs_in->arr[ii], mode64 );
       EMIT_INSTR( instrs_in->arr[ii] );
 
 #     if DEBUG_REGALLOC

diff --git a/VEX/priv/host-ppc32/hdefs.c b/VEX/priv/host-ppc32/hdefs.c
index 9ffe1df111678dd902d48ab3728814680a94185e..78241178b5b631036f60f440d5747ef50bb7589d 100644 (file)
--- a/VEX/priv/host-ppc32/hdefs.c
+++ b/VEX/priv/host-ppc32/hdefs.c
@@ -189,7 +189,7 @@ HReg hregPPC32_VR29 ( void ) { return mkHReg(29, HRcVec128, False); }
 HReg hregPPC32_VR30 ( void ) { return mkHReg(30, HRcVec128, False); }
 HReg hregPPC32_VR31 ( void ) { return mkHReg(31, HRcVec128, False); }
 
-void getAllocableRegs_PPC32 ( Int* nregs, HReg** arr )
+void getAllocableRegs_PPC32 ( Int* nregs, HReg** arr, Bool mode64 )
 {
    UInt i=0;
    *nregs = 90 - 24 - 24;
@@ -1088,7 +1088,7 @@ static void ppMovReg ( HReg dst, HReg src ) {
    }
 }
 
-void ppPPC32Instr ( PPC32Instr* i )
+void ppPPC32Instr ( PPC32Instr* i, Bool mode64 )
 {
    switch (i->tag) {
    case Pin_LI32:
@@ -1510,7 +1510,7 @@ void ppPPC32Instr ( PPC32Instr* i )
 
 /* --------- Helpers for register allocation. --------- */
 
-void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i )
+void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i, Bool mode64 )
 {
    initHRegUsage(u);
    switch (i->tag) {
@@ -1734,18 +1734,18 @@ void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i )
       return;
 
    default:
-      ppPPC32Instr(i);
+      ppPPC32Instr(i, mode64);
       vpanic("getRegUsage_PPC32Instr");
    }
 }
 
 /* local helper */
-static void mapReg(HRegRemap* m, HReg* r)
+static void mapReg( HRegRemap* m, HReg* r )
 {
    *r = lookupHRegRemap(m, *r);
 }
 
-void mapRegs_PPC32Instr (HRegRemap* m, PPC32Instr* i)
+void mapRegs_PPC32Instr ( HRegRemap* m, PPC32Instr* i, Bool mode64 )
 {
    switch (i->tag) {
    case Pin_LI32:
@@ -1907,7 +1907,7 @@ void mapRegs_PPC32Instr (HRegRemap* m, PPC32Instr* i)
       return;
 
    default:
-      ppPPC32Instr(i);
+      ppPPC32Instr(i, mode64);
       vpanic("mapRegs_PPC32Instr");
    }
 }
@@ -1946,7 +1946,7 @@ Bool isMove_PPC32Instr ( PPC32Instr* i, HReg* src, HReg* dst )
 /* Generate ppc32 spill/reload instructions under the direction of the
    register allocator.  Note it's critical these don't write the
    condition codes. */
-PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB )
+PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB, Bool mode64 )
 {
    PPC32AMode* am;
    vassert(!hregIsVirtual(rreg));
@@ -1966,7 +1966,7 @@ PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB )
    }
 }
 
-PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB )
+PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB, Bool mode64 )
 {
    PPC32AMode* am;
    vassert(!hregIsVirtual(rreg));
@@ -2286,13 +2286,13 @@ static UChar* mkFormVA ( UChar* p, UInt opc1, UInt r1, UInt r2,
    Note that buf is not the insn's final place, and therefore it is
    imperative to emit position-independent code. */
 
-Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i )
+Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i, Bool mode64 )
 {
    UChar* p = &buf[0];
    UChar* ptmp = p;
    vassert(nbuf >= 32);
 
-//   vex_printf("asm  ");ppPPC32Instr(i); vex_printf("\n");
+//   vex_printf("asm  ");ppPPC32Instr(i, mode64); vex_printf("\n");
 
    switch (i->tag) {
 
@@ -3295,7 +3295,7 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i )
 
   bad:
    vex_printf("\n=> ");
-   ppPPC32Instr(i);
+   ppPPC32Instr(i, mode64);
    vpanic("emit_PPC32Instr");
    /*NOTREACHED*/
    

diff --git a/VEX/priv/host-ppc32/hdefs.h b/VEX/priv/host-ppc32/hdefs.h
index e210a8c0052b6494e5187b5f6e360950c1301605..4d56a22e24be85f82f01e9698a15e2644233c246 100644 (file)
--- a/VEX/priv/host-ppc32/hdefs.h
+++ b/VEX/priv/host-ppc32/hdefs.h
@@ -774,17 +774,17 @@ extern PPC32Instr* PPC32Instr_AvSplat    ( UChar sz, HReg dst, PPC32VI5s* src );
 extern PPC32Instr* PPC32Instr_AvCMov     ( PPC32CondCode, HReg dst, HReg src );
 extern PPC32Instr* PPC32Instr_AvLdVSCR   ( HReg src );
 
-extern void ppPPC32Instr ( PPC32Instr* );
+extern void ppPPC32Instr ( PPC32Instr*, Bool mode64 );
 
 /* Some functions that insulate the register allocator from details
    of the underlying instruction set. */
-extern void         getRegUsage_PPC32Instr ( HRegUsage*, PPC32Instr* );
-extern void         mapRegs_PPC32Instr     ( HRegRemap*, PPC32Instr* );
+extern void         getRegUsage_PPC32Instr ( HRegUsage*, PPC32Instr*, Bool mode64 );
+extern void         mapRegs_PPC32Instr     ( HRegRemap*, PPC32Instr* , Bool mode64);
 extern Bool         isMove_PPC32Instr      ( PPC32Instr*, HReg*, HReg* );
-extern Int          emit_PPC32Instr        ( UChar* buf, Int nbuf, PPC32Instr* );
-extern PPC32Instr*  genSpill_PPC32         ( HReg rreg, UShort offsetB );
-extern PPC32Instr*  genReload_PPC32        ( HReg rreg, UShort offsetB );
-extern void         getAllocableRegs_PPC32 ( Int*, HReg** );
+extern Int          emit_PPC32Instr        ( UChar* buf, Int nbuf, PPC32Instr*, Bool mode64 );
+extern PPC32Instr*  genSpill_PPC32         ( HReg rreg, UShort offsetB, Bool mode64 );
+extern PPC32Instr*  genReload_PPC32        ( HReg rreg, UShort offsetB, Bool mode64 );
+extern void         getAllocableRegs_PPC32 ( Int*, HReg**, Bool mode64 );
 extern HInstrArray* iselBB_PPC32           ( IRBB*, VexArchInfo* );
 
 #endif /* ndef __LIBVEX_HOST_PPC32_HDEFS_H */

diff --git a/VEX/priv/host-ppc32/isel.c b/VEX/priv/host-ppc32/isel.c
index 50ad83838e2038028ab6db03ed75e807a237feac..da3e46c1031b7be2e016fd723307544767f0a9e9 100644 (file)
--- a/VEX/priv/host-ppc32/isel.c
+++ b/VEX/priv/host-ppc32/isel.c
@@ -209,7 +209,7 @@ static void addInstr ( ISelEnv* env, PPC32Instr* instr )
 {
    addHInstr(env->code, instr);
    if (vex_traceflags & VEX_TRACE_VCODE) {
-      ppPPC32Instr(instr);
+      ppPPC32Instr(instr, False);
       vex_printf("\n");
    }
 }

diff --git a/VEX/priv/host-x86/hdefs.c b/VEX/priv/host-x86/hdefs.c
index 334899a4f32ef4b94480b5e21627572eb7abbc8e..8471492e2c8318e1326200712256d8dee266ddea 100644 (file)
--- a/VEX/priv/host-x86/hdefs.c
+++ b/VEX/priv/host-x86/hdefs.c
@@ -877,7 +877,8 @@ X86Instr* X86Instr_SseShuf ( Int order, HReg src, HReg dst ) {
    return i;
 }
 
-void ppX86Instr ( X86Instr* i ) {
+void ppX86Instr ( X86Instr* i, Bool mode64 ) {
+   vassert(mode64 == False);
    switch (i->tag) {
       case Xin_Alu32R:
          vex_printf("%sl ", showX86AluOp(i->Xin.Alu32R.op));
@@ -1128,9 +1129,10 @@ void ppX86Instr ( X86Instr* i ) {
 
 /* --------- Helpers for register allocation. --------- */
 
-void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i)
+void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i, Bool mode64)
 {
    Bool unary;
+   vassert(mode64 == False);
    initHRegUsage(u);
    switch (i->tag) {
       case Xin_Alu32R:
@@ -1348,19 +1350,20 @@ void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i)
          addHRegUse(u, HRmWrite, i->Xin.SseShuf.dst);
          return;
       default:
-         ppX86Instr(i);
+         ppX86Instr(i, False);
          vpanic("getRegUsage_X86Instr");
    }
 }
 
 /* local helper */
-static void mapReg(HRegRemap* m, HReg* r)
+static void mapReg( HRegRemap* m, HReg* r )
 {
    *r = lookupHRegRemap(m, *r);
 }
 
-void mapRegs_X86Instr (HRegRemap* m, X86Instr* i)
+void mapRegs_X86Instr ( HRegRemap* m, X86Instr* i, Bool mode64 )
 {
+   vassert(mode64 == False);
    switch (i->tag) {
       case Xin_Alu32R:
          mapRegs_X86RMI(m, i->Xin.Alu32R.src);
@@ -1493,7 +1496,7 @@ void mapRegs_X86Instr (HRegRemap* m, X86Instr* i)
          mapReg(m, &i->Xin.SseShuf.dst);
          return;
       default:
-         ppX86Instr(i);
+         ppX86Instr(i, mode64);
          vpanic("mapRegs_X86Instr");
    }
 }
@@ -1537,11 +1540,12 @@ Bool isMove_X86Instr ( X86Instr* i, HReg* src, HReg* dst )
    register allocator.  Note it's critical these don't write the
    condition codes. */
 
-X86Instr* genSpill_X86 ( HReg rreg, Int offsetB )
+X86Instr* genSpill_X86 ( HReg rreg, Int offsetB, Bool mode64 )
 {
    X86AMode* am;
    vassert(offsetB >= 0);
    vassert(!hregIsVirtual(rreg));
+   vassert(mode64 == False);
    am = X86AMode_IR(offsetB, hregX86_EBP());
 
    switch (hregClass(rreg)) {
@@ -1557,11 +1561,12 @@ X86Instr* genSpill_X86 ( HReg rreg, Int offsetB )
    }
 }
 
-X86Instr* genReload_X86 ( HReg rreg, Int offsetB )
+X86Instr* genReload_X86 ( HReg rreg, Int offsetB, Bool mode64 )
 {
    X86AMode* am;
    vassert(offsetB >= 0);
    vassert(!hregIsVirtual(rreg));
+   vassert(mode64 == False);
    am = X86AMode_IR(offsetB, hregX86_EBP());
    switch (hregClass(rreg)) {
       case HRcInt32:
@@ -1827,7 +1832,7 @@ static UChar* push_word_from_tags ( UChar* p, UShort tags )
    Note that buf is not the insn's final place, and therefore it is
    imperative to emit position-independent code. */
 
-Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i )
+Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i, Bool mode64 )
 {
    UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc;
 
@@ -1835,13 +1840,14 @@ Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i )
    UChar* p = &buf[0];
    UChar* ptmp;
    vassert(nbuf >= 32);
+   vassert(mode64 == False);
 
    /* Wrap an integer as a int register, for use assembling
       GrpN insns, in which the greg field is used as a sub-opcode
       and does not really contain a register. */
 #  define fake(_n) mkHReg((_n), HRcInt32, False)
 
-   /* vex_printf("asm  ");ppX86Instr(i); vex_printf("\n"); */
+   /* vex_printf("asm  ");ppX86Instr(i, mode64); vex_printf("\n"); */
 
    switch (i->tag) {
 
@@ -2815,7 +2821,7 @@ Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i )
    }
 
   bad:
-   ppX86Instr(i);
+   ppX86Instr(i, mode64);
    vpanic("emit_X86Instr");
    /*NOTREACHED*/
    

diff --git a/VEX/priv/host-x86/hdefs.h b/VEX/priv/host-x86/hdefs.h
index 0a35c876281655e85fc4cd1cc1b099eace57e472..28346c2a07c2dab949d9539c7e204cf0757adae0 100644 (file)
--- a/VEX/priv/host-x86/hdefs.h
+++ b/VEX/priv/host-x86/hdefs.h
@@ -653,16 +653,16 @@ extern X86Instr* X86Instr_SseCMov   ( X86CondCode, HReg src, HReg dst );
 extern X86Instr* X86Instr_SseShuf   ( Int order, HReg src, HReg dst );
 
 
-extern void ppX86Instr ( X86Instr* );
+extern void ppX86Instr ( X86Instr*, Bool );
 
 /* Some functions that insulate the register allocator from details
    of the underlying instruction set. */
-extern void         getRegUsage_X86Instr ( HRegUsage*, X86Instr* );
-extern void         mapRegs_X86Instr     ( HRegRemap*, X86Instr* );
+extern void         getRegUsage_X86Instr ( HRegUsage*, X86Instr*, Bool );
+extern void         mapRegs_X86Instr     ( HRegRemap*, X86Instr*, Bool );
 extern Bool         isMove_X86Instr      ( X86Instr*, HReg*, HReg* );
-extern Int          emit_X86Instr        ( UChar* buf, Int nbuf, X86Instr* );
-extern X86Instr*    genSpill_X86         ( HReg rreg, Int offset );
-extern X86Instr*    genReload_X86        ( HReg rreg, Int offset );
+extern Int          emit_X86Instr        ( UChar* buf, Int nbuf, X86Instr*, Bool );
+extern X86Instr*    genSpill_X86         ( HReg rreg, Int offset, Bool );
+extern X86Instr*    genReload_X86        ( HReg rreg, Int offset, Bool );
 extern void         getAllocableRegs_X86 ( Int*, HReg** );
 extern HInstrArray* iselBB_X86           ( IRBB*, VexArchInfo* );
 

diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c
index 71763dd7a4ed1955bf3d32aeff5861bdf2f5dac0..50fb29a59fdfe49f415229afdf64eaf0f99c56fb 100644 (file)
--- a/VEX/priv/host-x86/isel.c
+++ b/VEX/priv/host-x86/isel.c
@@ -183,7 +183,7 @@ static void addInstr ( ISelEnv* env, X86Instr* instr )
 {
    addHInstr(env->code, instr);
    if (vex_traceflags & VEX_TRACE_VCODE) {
-      ppX86Instr(instr);
+      ppX86Instr(instr, False);
       vex_printf("\n");
    }
 }

diff --git a/VEX/priv/main/vex_main.c b/VEX/priv/main/vex_main.c
index 7d453addd691fb5317256364549ac7b6cb1be693..37bd709d03a66e33e97f8961144a268c1a63ae28 100644 (file)
--- a/VEX/priv/main/vex_main.c
+++ b/VEX/priv/main/vex_main.c
@@ -215,15 +215,15 @@ VexTranslateResult LibVEX_Translate (
       from the target instruction set. */
    HReg* available_real_regs;
    Int   n_available_real_regs;
-   Bool         (*isMove)      (HInstr*, HReg*, HReg*);
-   void         (*getRegUsage) (HRegUsage*, HInstr*);
-   void         (*mapRegs)     (HRegRemap*, HInstr*);
-   HInstr*      (*genSpill)    ( HReg, Int );
-   HInstr*      (*genReload)   ( HReg, Int );
-   void         (*ppInstr)     ( HInstr* );
+   Bool         (*isMove)      ( HInstr*, HReg*, HReg* );
+   void         (*getRegUsage) ( HRegUsage*, HInstr*, Bool );
+   void         (*mapRegs)     ( HRegRemap*, HInstr*, Bool );
+   HInstr*      (*genSpill)    ( HReg, Int, Bool );
+   HInstr*      (*genReload)   ( HReg, Int, Bool );
+   void         (*ppInstr)     ( HInstr*, Bool );
    void         (*ppReg)       ( HReg );
    HInstrArray* (*iselBB)      ( IRBB*, VexArchInfo* );
-   Int          (*emit)        ( UChar*, Int, HInstr* );
+   Int          (*emit)        ( UChar*, Int, HInstr*, Bool );
    IRExpr*      (*specHelper)  ( HChar*, IRExpr** );
    Bool         (*preciseMemExnsFn) ( Int, Int );
 
@@ -239,6 +239,7 @@ VexTranslateResult LibVEX_Translate (
    UChar           insn_bytes[32];
    IRType          guest_word_type;
    IRType          host_word_type;
+   Bool            mode64;
 
    guest_layout           = NULL;
    available_real_regs    = NULL;
@@ -259,6 +260,7 @@ VexTranslateResult LibVEX_Translate (
    host_word_type         = Ity_INVALID;
    offB_TISTART           = 0;
    offB_TILEN             = 0;
+   mode64                 = False;
 
    vex_traceflags = traceflags;
 
@@ -272,17 +274,18 @@ VexTranslateResult LibVEX_Translate (
    switch (arch_host) {
 
       case VexArchX86:
+         mode64      = False;
          getAllocableRegs_X86 ( &n_available_real_regs,
                                 &available_real_regs );
          isMove      = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr;
-         getRegUsage = (void(*)(HRegUsage*,HInstr*)) getRegUsage_X86Instr;
-         mapRegs     = (void(*)(HRegRemap*,HInstr*)) mapRegs_X86Instr;
-         genSpill    = (HInstr*(*)(HReg,Int)) genSpill_X86;
-         genReload   = (HInstr*(*)(HReg,Int)) genReload_X86;
-         ppInstr     = (void(*)(HInstr*)) ppX86Instr;
+         getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_X86Instr;
+         mapRegs     = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr;
+         genSpill    = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86;
+         genReload   = (HInstr*(*)(HReg,Int, Bool)) genReload_X86;
+         ppInstr     = (void(*)(HInstr*, Bool)) ppX86Instr;
          ppReg       = (void(*)(HReg)) ppHRegX86;
          iselBB      = iselBB_X86;
-         emit        = (Int(*)(UChar*,Int,HInstr*)) emit_X86Instr;
+         emit        = (Int(*)(UChar*,Int,HInstr*, Bool)) emit_X86Instr;
          host_is_bigendian = False;
          host_word_type    = Ity_I32;
          vassert(archinfo_host->subarch == VexSubArchX86_sse0
@@ -291,34 +294,36 @@ VexTranslateResult LibVEX_Translate (
          break;
 
       case VexArchAMD64:
+         mode64      = True;
          getAllocableRegs_AMD64 ( &n_available_real_regs,
                                   &available_real_regs );
          isMove      = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr;
-         getRegUsage = (void(*)(HRegUsage*,HInstr*)) getRegUsage_AMD64Instr;
-         mapRegs     = (void(*)(HRegRemap*,HInstr*)) mapRegs_AMD64Instr;
-         genSpill    = (HInstr*(*)(HReg,Int)) genSpill_AMD64;
-         genReload   = (HInstr*(*)(HReg,Int)) genReload_AMD64;
-         ppInstr     = (void(*)(HInstr*)) ppAMD64Instr;
+         getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_AMD64Instr;
+         mapRegs     = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr;
+         genSpill    = (HInstr*(*)(HReg,Int, Bool)) genSpill_AMD64;
+         genReload   = (HInstr*(*)(HReg,Int, Bool)) genReload_AMD64;
+         ppInstr     = (void(*)(HInstr*, Bool)) ppAMD64Instr;
          ppReg       = (void(*)(HReg)) ppHRegAMD64;
          iselBB      = iselBB_AMD64;
-         emit        = (Int(*)(UChar*,Int,HInstr*)) emit_AMD64Instr;
+         emit        = (Int(*)(UChar*,Int,HInstr*, Bool)) emit_AMD64Instr;
          host_is_bigendian = False;
          host_word_type    = Ity_I64;
          vassert(archinfo_host->subarch == VexSubArch_NONE);
          break;
 
       case VexArchPPC32:
+         mode64      = False;
          getAllocableRegs_PPC32 ( &n_available_real_regs,
-                                  &available_real_regs );
+                                  &available_real_regs, mode64 );
          isMove      = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPC32Instr;
-         getRegUsage = (void(*)(HRegUsage*,HInstr*)) getRegUsage_PPC32Instr;
-         mapRegs     = (void(*)(HRegRemap*,HInstr*)) mapRegs_PPC32Instr;
-         genSpill    = (HInstr*(*)(HReg,Int)) genSpill_PPC32;
-         genReload   = (HInstr*(*)(HReg,Int)) genReload_PPC32;
-         ppInstr     = (void(*)(HInstr*)) ppPPC32Instr;
+         getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPC32Instr;
+         mapRegs     = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPC32Instr;
+         genSpill    = (HInstr*(*)(HReg,Int,Bool)) genSpill_PPC32;
+         genReload   = (HInstr*(*)(HReg,Int,Bool)) genReload_PPC32;
+         ppInstr     = (void(*)(HInstr*,Bool)) ppPPC32Instr;
          ppReg       = (void(*)(HReg)) ppHRegPPC32;
          iselBB      = iselBB_PPC32;
-         emit        = (Int(*)(UChar*,Int,HInstr*)) emit_PPC32Instr;
+         emit        = (Int(*)(UChar*,Int,HInstr*,Bool)) emit_PPC32Instr;
          host_is_bigendian = True;
          host_word_type    = Ity_I32;
          vassert(archinfo_guest->subarch == VexSubArchPPC32_I
@@ -553,7 +558,7 @@ VexTranslateResult LibVEX_Translate (
    if (vex_traceflags & VEX_TRACE_VCODE) {
       for (i = 0; i < vcode->arr_used; i++) {
          vex_printf("%3d   ", i);
-         ppInstr(vcode->arr[i]);
+         ppInstr(vcode->arr[i], mode64);
          vex_printf("\n");
       }
       vex_printf("\n");
@@ -564,7 +569,7 @@ VexTranslateResult LibVEX_Translate (
                                            n_available_real_regs,
                                   isMove, getRegUsage, mapRegs, 
                                   genSpill, genReload, guest_sizeB,
-                                  ppInstr, ppReg );
+                                  ppInstr, ppReg, mode64 );
 
    vexAllocSanityCheck();
 
@@ -574,7 +579,7 @@ VexTranslateResult LibVEX_Translate (
                    "------------------------\n\n");
       for (i = 0; i < rcode->arr_used; i++) {
          vex_printf("%3d   ", i);
-         ppInstr(rcode->arr[i]);
+         ppInstr(rcode->arr[i], mode64);
          vex_printf("\n");
       }
       vex_printf("\n");
@@ -594,10 +599,10 @@ VexTranslateResult LibVEX_Translate (
    out_used = 0; /* tracks along the host_bytes array */
    for (i = 0; i < rcode->arr_used; i++) {
       if (vex_traceflags & VEX_TRACE_ASM) {
-         ppInstr(rcode->arr[i]);
+         ppInstr(rcode->arr[i], mode64);
          vex_printf("\n");
       }
-      j = (*emit)( insn_bytes, 32, rcode->arr[i] );
+      j = (*emit)( insn_bytes, 32, rcode->arr[i], mode64 );
       if (vex_traceflags & VEX_TRACE_ASM) {
          for (k = 0; k < j; k++)
             if (insn_bytes[k] < 16)