clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750

Update the force mem core bit for UFS AXI clock to force the core on
signal to remain active during halt state of the clk. If force mem
core bit of the clock is not set, the memories of the subsystem will
not retain the logic across power states. This is required for the MCQ
feature of the UFS driver.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-1-67b5529b9b5d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index fa1672c4e7d814e1e08c79f9cda9463bf1cd1598..24f98062b9dd50f8397dab8392fff45051ab3665 100644 (file)
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -3817,7 +3817,9 @@ static int gcc_sm8650_probe(struct platform_device *pdev)
        qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
        qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
 
+       /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
        qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+       qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
 
        /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
        regmap_write(regmap, 0x52150, 0x0);

diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
index b36d70976095834ae4f7936d83f228d81b2c31e8..8092dd6b37b56f4fd786e33d4f0e8aabcd6ecdfe 100644 (file)
--- a/drivers/clk/qcom/gcc-sm8750.c
+++ b/drivers/clk/qcom/gcc-sm8750.c
@@ -3244,8 +3244,9 @@ static int gcc_sm8750_probe(struct platform_device *pdev)
        regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
        regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
 
-       /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
+       /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
        qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+       qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
 
        return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
 }