iTCO_wdt: mask NMI_NOW bit for update_no_reboot_bit() call

Commit da23b6faa8bf ("watchdog: iTCO: Add support for Cannon Lake
PCH iTCO") does not mask NMI_NOW bit during TCO1_CNT register's
value comparison for update_no_reboot_bit() call causing following
failure:

   ...
   iTCO_vendor_support: vendor-support=0
   iTCO_wdt iTCO_wdt: unable to reset NO_REBOOT flag, device
                                    disabled by hardware/BIOS
   ...

and this can lead to unexpected NMIs later during regular
crashkernel's workflow because of watchdog probe call failures.

This change masks NMI_NOW bit for TCO1_CNT register values to
avoid unexpected NMI_NOW bit inversions.

Fixes: da23b6faa8bf ("watchdog: iTCO: Add support for Cannon Lake PCH iTCO")
Signed-off-by: Oleksandr Ocheretnyi <oocheret@cisco.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20240913191403.2560805-1-oocheret@cisco.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index 35b358bcf94ce68fdb80d57ed4da760f09a14d18..f01ed38aba67517d28321c7159e4e3bbb2896f6c 100644 (file)
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -82,6 +82,13 @@
 #define TCO2_CNT(p)    (TCOBASE(p) + 0x0a) /* TCO2 Control Register    */
 #define TCOv2_TMR(p)   (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
 
+/*
+ * NMI_NOW is bit 8 of TCO1_CNT register
+ * Read/Write
+ * This bit is implemented as RW but has no effect on HW.
+ */
+#define NMI_NOW                BIT(8)
+
 /* internal variables */
 struct iTCO_wdt_private {
        struct watchdog_device wddev;
@@ -219,13 +226,23 @@ static int update_no_reboot_bit_cnt(void *priv, bool set)
        struct iTCO_wdt_private *p = priv;
        u16 val, newval;
 
-       val = inw(TCO1_CNT(p));
+       /*
+        * writing back 1b1 to NMI_NOW of TCO1_CNT register
+        * causes NMI_NOW bit inversion what consequently does
+        * not allow to perform the register's value comparison
+        * properly.
+        *
+        * NMI_NOW bit masking for TCO1_CNT register values
+        * helps to avoid possible NMI_NOW bit inversions on
+        * following write operation.
+        */
+       val = inw(TCO1_CNT(p)) & ~NMI_NOW;
        if (set)
                val |= BIT(0);
        else
                val &= ~BIT(0);
        outw(val, TCO1_CNT(p));
-       newval = inw(TCO1_CNT(p));
+       newval = inw(TCO1_CNT(p)) & ~NMI_NOW;
 
        /* make sure the update is successful */
        return val != newval ? -EIO : 0;