clk: meson-g12a: add missing fclk_div2 to spicc

SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes
are wrong on this clock. This causes the spicc module to output sclk at
2.5x the expected rate when clock index 3 is picked.

Adding the missing fclk_div2 resolves this.

[jbrunet: amended commit description]
Fixes: a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")
Cc: stable@vger.kernel.org # 6.1
Signed-off-by: Da Xue <da@libre.computer>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20250512142617.2175291-1-da@libre.computer
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index ceabebb1863d6ed93c157f036958ac55156bb0d9..d9e546e006d7e0b2af92fbcbb35498a00bd2fc6d 100644 (file)
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -4093,6 +4093,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = {
        { .hw = &g12a_clk81.hw },
        { .hw = &g12a_fclk_div4.hw },
        { .hw = &g12a_fclk_div3.hw },
+       { .hw = &g12a_fclk_div2.hw },
        { .hw = &g12a_fclk_div5.hw },
        { .hw = &g12a_fclk_div7.hw },
 };